The branch 'riscv/heads/gcc-15-with-riscv-opts' was updated to point to:
5f4072126dde... doc, riscv: Clean up documentation of RISC-V options [PR122
It previously pointed to:
b9f8770053cc... [PR rtl-optimization/122575] Fix mode on optimized IOR comp
Diff:
!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
-------------------------------------------------------------------
b9f8770... [PR rtl-optimization/122575] Fix mode on optimized IOR comp
5ed1d1e... RISC-V: Add test for vec_duplicate + vmsne.vv combine case
bc1653c... RISC-V: Add test for vec_duplicate + vmsne.vv combine case
059098a... [RISC-V] Avoid most calls to gen_extend_insn
633fb13... [RISC-V] Drop scan-tests of marginal value
41ebc96... RISC-V: Add missing member for andes_25_tune_info
7de00b4... Handle shift-pairs in ext-dce for targets without zero/sign
eb65a51... [RISC-V][PR rtl-optimization/122627] Yet another fix in IRA
2b639fd... RISC-V: Add Andes 25 series pipeline description.
e57a5d0... [RISC-V] Improve detection of packw
097d4b8... [RISC-V] Simplify riscv_extend_to_xmode_reg
5cb4a1b... RISC-V: Add test for vec_duplicate + vmseq.vv combine case
21b8399... RISC-V: Add test for vec_duplicate + vmseq.vv combine case
eb2dadc... [RISC-V] Add testcase for shifted truthvalue
49a556b... RISC-V: Combine vsext.vf2 and vsll.vi to vwsll.vi on ZVBB
ef0c01c... RISC-V: Add test for vec_duplicate + vwmaccu.vv combine wit
2f77eea... RISC-V: RISC-V: Combine vec_duplicate + vwmaccu.vv to vwmac
78247a3... [RISC-V] Ignore useless zero-initialization in conditional
e25d12b... [RISC-V][PR 121136] Improve various tests which only need t
b9cc894... RISC-V: testsuite: Fix pr119115.c.
8a41790... [PR rtl-optimization/122536] Fix guard against variable bit
7c1c6dc... RISC-V: Fix the ABI of empty unions and zero length array i
0f696a5... [RISC-V][PR tree-optimization/52345] Optimize testing multi
69c14c3... [RISC-V] Expose sign extension for 32 bit rotates by consta
c47fb95... gcc: Drop junk vim backup file
f34fabb... [RISC-V][SH][PR rtl-optimization/67731] Improve logical IOR
d650cfd... [RISC-V] Reorder ready queue slightly to avoid unnecessary
c4ab45c... niter: Use ranger to query ctz range.
b58620d... [PATCH v2] RISC-V: avlprop: Scale AVL by subreg ratio [PR12
764cc65... RISC-V: Clean up build warnings for VLS calling convention
b12adbc... Skip riscv/rvv/xtheadvector/pr116593.C if not hostedlib
0c4eb2e... RISC-V: Add testsuite for fixed-length vector calling conve
c9cf3b1... RISC-V: Add testsuite for fixed-length vector calling conve
cea619a... RISC-V: Implement standard fixed-length vector calling conv
d933f1a... [RISC-V][PR target/64345][PR tree-optimization/80770] Impro
5c37281... Increase NUM_ABI_IDS to support RISC-V VLS calling conventi
524de2c... [PATCH v2] RISC-V: Fix moving data from V_REGS to GR_REGS b
8592daf... Fix minor RISC-V testsuite failure
2025d31... Fix minor testsuite scan failures for RISC-V
e79b74f... RISC-V: Add testcase for unsigned scalar SAT_MUL form 6
97b5c1d... RISC-V: Fix incorrect op of vwaddu/vwsubu wx combine
e059d4b... [PATCH v3] RISC-V: Implement RISC-V profile macro support
48acd75... [RISC-V][PR target/120811] Improving address reloads in LRA
87cf04d... [PR target/119587] RISC-V: xtheadmemidx: Split slli.uw patt
bf59675... [RISC-V] Improve subword atomic patterns in sync.md
f7b7714... RISC-V: Add test for vec_duplicate + vwsubu.wv combine with
5208086... RISC-V: Combine vec_duplicate + vwsubu.wv to vwsubu.wx on G
5a758e9... RISC-V: Allow VLS types using up to LMUL 8
ffd88ce... [PATCH] RISC-V: Fix slide pattern recognition [PR122124]
2c17dc4... RISC-V: Combine vec_duplicate + vwaddu.wv to vwaddu.wx on G
cd279de... ISC-V: Add test for vec_duplicate + vwaddu.wv signed combin
2820c2f... Fixup merge conflict
b29241a... [PATCH v2] RISC-V: Fix type of CFA during stack probe [PR12
37e5606... [RISC-V][PR target/122147] Avoid creating (subreg (mem)) in
eb239c5... [PR target/118945][PATCH v3] RISC-V: Add 'prefer_agnostic'
6b730ee... [RISC-V][PR rtl-optimization/121937] Don't call neg_poly_in
9b79a0e... [RISC-V][PR target/122051] Fix pmode_reg_or_uimm5_operand f
eca3615... [RISC-V][PR target/122106] Add missing predicate on crc exp
1f3af2a... [PATCH][PR target/121778] RISC-V: Improve rotation detectio
3e45271... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
a0ea965... RISC-V: Add missing define_insn_reservation to tt-ascalon-d
c2b587f... [RISC-V][PR target/121983] Fix unprotected REGNO invocation
8a1e591... RISC-V: Improve slide patterns recognition
9e71740... RISC-V: Only Save/Restore required registers for ILP32E/LP6
399946d... [RISC-V] Optimize clear-lowest-set-bit sequence when ctz is
ef71f3f... RISC-V: Correct lmul estimation
1ad8b60... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
c8681e0... [PR tree-optimization/58727] Don't over-simplify constants`
14b011a... RISC-V: Add test for vec_duplicate + vwmulu.vv signed combi
16405b3... RISC-V: Add test for vec_duplicate + vwsubu.vv signed combi
6110a72... RISC-V: Add test for vec_duplicate + vwaddu.vv signed combi
28604e9... RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on G
c35b44c... RISC-V: Allow profiles input in '--with-arch' option.
b0d7b51... RISC-V: Configure Profiles definitions in the definition fi
53a8649... RISC-V: Imply zicsr for sdtrig and ssstrict extensions.
82646da... Widening-Mul: Refine build_and_insert_cast when rhs is cast
19ac053... RISC-V: Fix vendor intrinsic tests for disabled multilib co
52c3602... RISC-V: Support vnclip idiom testcase [PR120378]
4add0df... Match: Support SAT_TRUNC variant NARROW_CLIP
61b4776... [RISC-V] Adjust ABI specification in recently added Andes t
738d515... RISC-V: Suppress cross CC sibcall optimization from vector
c2baf8d... RISC-V: Add min/max patterns for ifcvt.
503fcdc... ifcvt: Clarify if_info.original_cost.
e071943... RISC-V: Fix can_find_related_mode_p for VLS types
d3adcee... RISC-V: Fix typo in tt-ascalon-d8's pipeline description [P
951b71c... RISC-V: Add pattern for vector-scalar single widening float
d34b34d... RISC-V: Add pattern for vector-scalar dual widening floatin
4b9d183... RISC-V: Add pattern for vector-scalar single widening float
0674ceb... RISC-V: Add pattern for vector-scalar widening floating-poi
0202e91... RISC-V: Adjust tt-ascalon-d8 branch cost
0ce7c88... RISC-V: Add pattern for vector-scalar single-width floating
51614ae... RISC-V: Add pattern for vector-scalar single-width floating
e385344... RISC-V: Add pattern for vector-scalar single-width floating
7ad7d8c... RISC-V: Add pattern for vector-scalar widening floating-poi
c90bdc6... RISC-V: Add patterns for vector-scalar IEEE floating-point
023ccbf... gcc: introduce the dep_fusion pass
c3c15eb... RISC-V: Add support for the XAndesvdot ISA extension.
1af85ce... [RISC-V] Fix ordering of pipeline models
523b318... RISC-V: Add support for the XAndesvpackfph ISA extension.
15174fb... RISC-V: Add test for vec_duplicate + vnmsub.vv unsigned com
fd92765... RISC-V: Add test for vec_duplicate + vnmsub.vv signed combi
0fac516... RISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub.vx on G
7611357... dep_fusion: Fix if target does not have macro fusion [PR121
4237e95... gcc: introduce the dep_fusion pass
1b157cd... RISC-V: Add support for the XAndesvsintload ISA extension.
06561ca... RISC-V: Add support for the XAndesvbfhcvt ISA extension.
1b5374b... RISC-V: Add tt-ascalon-d8 pipeline description
186039c... [RISC-V] Adjust recently added test
55565fd... RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2
9eb00cd... RISC-V: Allow errors to be suppressed when parsing architec
c9b62a5... RISC-V: Adjust the vmacc.vx combine test cases
7c76a52... RISC-V: Add test for vec_duplicate + vmadd.vv unsigned comb
a70aa7f... RISC-V: Add test for vec_duplicate + vmadd.vv signed combin
08e5b06... RISC-V: Fix extension subset check in riscv_can_inline_p
099b2e5... RISC-V: Add support for the XAndesbfhcvt ISA extension.
edab9d2... RISC-V: Add support for the XAndesperf ISA extension.
237471b... RISC-V: Add basic XAndes vendor extension support.
d69fa45... RISC-V: Add pattern for vector-scalar floating-point max
3f5b181... [RISC-V][PR target/121213] Avoid unnecessary sign extension
a527df8... RISC-V: Fix is_vlmax_len_p and use for strided ops.
e12dd4c... RISC-V: Add Zbb extension sext testcase.
eca0c44... RISC-V: Update Zba 'shNadd.uw' testcase.`
7d2ccb7... RISC-V: Remove unused print_ext_doc_entry function [NFC]
b848885... [RISC-V] Improve initial RTL generation for SImode adds on
1077d36... RISC-V: Add test case for unsigned scalar SAT_MUL form 4
68dc806... RISC-V: Add patterns for vector-scalar IEEE floating-point
cb6a9c9... RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned com
a44f6de... RISC-V: Add test for vec_duplicate + vnmsac.vv signed combi
1920d49... RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on G
b092154... RISC-V: Add pattern for vector-scalar floating-point min
a5b607a... Remove xfail marker on RISC-V test
16d9ee1... RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv
09cc9f8... More RISC-V testsuite hygiene
ef9893a... [committed] RISC-V Testsuite hygiene
4df0cb8... [PATCH] RISC-V: Add pattern for reverse floating-point divi
7140bbb... [PATCH] RISC-V: Add pattern for vector-scalar single-width
4f7b34c... Fix RISC-V bootstrap
fbaa711... RISC-V: Add test for vec_duplicate + vmacc.vv unsigned comb
4b9d8dd... RISC-V: Add test for vec_duplicate + vmacc.vv signed combin
ed331e7... RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2
a71bca7... RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE mac
f268cd4... Fix invalid right shift count with recent ifcvt changes
2be5287... [PR rtl-optimization/120553] Improve selecting between cons
3a66728... RISC-V: Add testcase for scalar unsigned SAT_MUL form 3
f9f705f... RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh
c35a012... [PR target/121213] Avoid unnecessary constant load in amosw
dd6dfcb... regrename: treat writes as reads for fused instruction pair
7964e52... ira: tie output allocnos for fused instruction pairs
7d1700f... [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR
d62ba04... RISC-V: Update the comments of vx combine [NFC]
f515dd7... RISC-V: Add missed DONE for vx combine pattern [NFC]
9ed4cb1... RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and ca
34b797c... [PR target/119275][RISC-V] Avoid calling gen_lowpart in cas
5f8f1f5... [RISC-V][PR target/121531] Cover missing insn types in p400
34e2bac... [RISC-V][PR target/121160] Avoid bogus force_reg call
06fdf31... [RISC-V][PR target/121113] Handle HFmode in various insn re
b2851be... RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm com
748b095... RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on G
7a6c62f... RISC-V: Expand const_vector with 2 elts per pattern.
9b861c7... Improve initial code generation for addsi/adddi
b3ebae3... Don't run tests requiring "B" on designs without "B"
72f09a0... RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
b93fd96... RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost
751098f... RISC-V: Read extension data from riscv-ext*.def for arch-ca
bed4514... RISC-V: Support -march=unset
5e8ee2d... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
b6a17bb... RISC-V: Add testcases for signed avg ceil vx combine
a7be247... RISC-V: Adding H to the canonical order [PR121312]
9b47062... RISC-V: Add testcases for unsigned avg ceil vx combine.
0621b49... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
d3f1692... RISC-V: Remove use of structured binding to fix compiler wa
b92595e... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
62be3ba... RISC-V: Add test case for vaadd.vx combine polluting VXRM
db2de38... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
6015839... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
90080eb... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
f7cbdde... RISC-V: Fix another vf FP16 combine run test failures
a12d8cf... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
577312c... RISC-V: Prepare dynamic LMUL heuristic for SLP.
a2cc047... RISC-V: Remove user-level interrupts
55119a0... RISC-V: Add support for resumable non-maskable interrupt (R
13826c1... riscv: testsuite: Fix misalignment check.
6bd7a23... RISC-V: Add test case for vx combine polluting VXRM
ea980ad... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
c032e32... RISC-V: Rework broadcast handling [PR121073].
7b1a826... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
1c8654d... Change bellow in comments to below
8e287b7... [RISC-V] Restrict generic-vector-ooo DFA
452b351... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
1df11ca... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
8ee5487... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
33accd2... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
2cb88af... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
fff4c08... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
64e67cf... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
3d41018... RISC-V: Refine the test case for vector avg_floor and avg_c
3620e65... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
6913dd0... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
f2140dc... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
4ab0159... RISC-V: Support RVVDImode for avg3_ceil auto vect
92b8d38... RISC-V: Fix vsetvl merge rule.
4b8124f... RISC-V: Refine the scalar SAT_* test cases
b8ba5b2... RISC-V: Support RVVDImode for avg3_floor auto vect
75111e5... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
ff8371e... RISC-V: Add testcase for rv32 SAT_MUL from uint64
83d354a... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
4ffac49... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
e51a9ad... RISC-V: Make zero-stride load broadcast a tunable.
97ab536... [RISC-V] Detect new fusions for RISC-V
d0297c1... RISCV: Remove the v extension requirement for sat scalar ru
4abfd77... RISC-V: Add test for vec_duplicate + vssub.vv combine case
0e095e0... RISC-V: Add test for vec_duplicate + vssub.vv combine case
9e1867e... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
488b4ba... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
118aff9... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
6ea699a... [RISC-V][PR target/120642] Avoid propagating constant AVL f
82ebbbe... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
5abbd77... RISC-V: Do not use vsetivli for THeadVector.
14f2195... RISC-V: Ignore non-types in builtin function hash.
b3b3f52... [committed][RISC-V] Fix testsuite fallout from check-functi
c6d0162... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
2497225... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
3b10f41... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
267bb15... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
394163e... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
378252c... [RISC-V] Add basic instrumentation to fusion detection
3ae5ced... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
e6f6302... Refactor record_function_versions.
303cd16... [RISC-V][PR target/118886] Refine when two insns are signal
11de7b0... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
c73aa74... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
a93e5b9... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
41a01b9... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
0f6f150... RISC-V: Reconcile the existing test due to cost model chang
0763090... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
f296fdc... RISC-V: Ignore -Oz for most rvv testcase [NFC]
6a3a4ad... RISC-V: Primary vector pipeline model for sifive 7 series
ef665de... RISC-V: Adding B ext, fp16 and missing scalar instruction t
41b544d... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
12abc86... RISC-V: Refactor the function bitmap_union_of_preds_with_en
701b8e4... RISC-V: Add pipeline-checker script
99044d8... [RISC-V][PR target/119971] Avoid losing shift count masking
403b8dd... RISC-V: update prepare_ternary_operands to handle vector-sc
cd04d09... RISC-V: Fix build issue
3407c78... RISC-V: Add comment and reorder the the include files in ri
e127335... RISC-V: Add Profiles RVA/B23S64 support.
f056ca8... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
68b7028... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
d605de9... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
cd6b075... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
e44e7ef... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
495cb9e... RISC-V: Fix ICE for expand_select_vldi [PR120652]
f786ba1... [RISC-V] Force several tests to use rocket tuning
d858c51... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
d1e26a9... RISC-V: Add test for vec_duplicate + vminu.vv combine case
6f5c281... RISC-V: Add test for vec_duplicate + vminu.vv combine case
74a44e1... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
dd9082d... RISC-V: Add generic tune as default.
baadc0f... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
b6c47d1... RISC-V: Adding cost model for zilsd
ff7641c... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
0eab021... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
d86789f... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
dca4700... [PATCH v1] RISC-V: Use scratch reg for loop control
0a20369... RISC-V: Add -fno-pie flags to testcases
2bf997f... RISC-V: Refine VX combine test case 0 to avoid code duplica
844c547... RISC-V: Update Profiles string in RV23.
e62fe3b... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
f185bd8... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
55f52e6... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
0a5fbfa... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
d2b56b6... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
5d00cb9... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
0a88e23... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
c5fb12e... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
b02625d... RISC-V: Prevent speculative vsetvl insn scheduling
c9fb4ae... RISC-V: Add patterns for vector-scalar negate-(multiply-add
c209747... RISC-V: testsuite: fix an obvious build error
090258c... RISC-V: Regen riscv-ext.texi [NFC]
fe6a0b0... RISC-V: Add test for vec_duplicate + vremu.vv combine case
740a05e... RISC-V: Add test for vec_duplicate + vremu.vv combine case
e76cd66... RISC-V: Reconcile the existing test for vremu.vx combine
e2277cd... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
ebee7f5... [RISC-V] Enable more if-conversion on RISC-V
e19a852... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
d1c0898... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
582f792... RISC-V: Reconcile the existing test for vrem.vx combine
f941708... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
c570bab... RISC-V: frm/mode-switch: robustify call_insn backtracking [
240e4c9... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
fe7e66f... RISC-V: frm/mode-switch: remove dubious frm edge insertion
c8a9931... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
10c3eb3... [RISC-V] Handle 32bit operands in condition for conditional
74132b8... [to-be-committed][RISC-V] Handle 32bit operands in conditio
594cdb5... RISC-V: Reconcile the existing test for vdivu.vx combine
efb12e0... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
4632b9b... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
b3393aa... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
b5af21b... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
51d8abf... [RISC-V] Improve signed division by 2^n
680d7b9... RISC-V: Don't use structured binding in riscv-common.cc
3df9ac6... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
edcad72... [RISC-V] Improve sequences to generate -1, 1 in some cases.
8326723... RISC-V: Support Ssu64xl extension.
cc34f59... RISC-V: Support Sstvecd extension.
2456f13... RISC-V: Support Sstvala extension.
0e04dd1... RISC-V: Support Sscounterenw extension.
38e23c1... RISC-V: Support Ssccptr extension.
049ed8e... RISC-V: Support Smrnmi extension.
fc30fcb... RISC-V: Support Sm/scsrind extensions.
6c6d4a9... RISC-V: Update extension defination.
3e2f5fd... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
fdee91b... [PATCH v2] RISC-V: Add svbare extension.
54a46f0... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
83eda48... RISC-V: Add Shlcofideleg extension.
dcb4f96... RISC-V: Reconcile the existing test for vdiv.vx combine
c6b888e... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
26f3a68... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
9421f64... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
286d1bb... RISC-V: Use helper function to get FPR to VR move cost
8c06b3d... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
9a0c151... [PATCH] RISC-V: Add smcntrpmf extension.
6aaf988... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
5e5b0d3... RISC-V: Implement full-featured iterator for riscv_subset_l
52b0728... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
d5088a7... RISC-V: Fix line too long format issue for autovect.md [NFC
9cd7639... RISC-V: Add test cases for avg_ceil vaadd implementation
b55ff59... RISC-V: Reconcile the existing test for avg_ceil
03f5f88... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
fd6e46c... RISC-V: Add minimal support of double trap extension 1.0
0b79926... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
8d59ceb... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
2ed7874... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
128ff99... RISC-V: Avoid division by zero in check_builtin_call [PR120
cdf244c... RISC-V: Add test cases for avg_floor vaadd implementation
ed0db9e... RISC-V: Reconcile the existing test for avg_floor
55be552... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
5fe5905... [RISC-V] Add andi+bclr synthesis
62756d5... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
4d87b9f... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
5271cc9... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
c3402a7... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
367fa41... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
1517e60... [RISC-V] shift+and+shift for logical and synthesis
92aaa9a... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
3282576... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
52489a6... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
9bf3f9e... RISC-V: Support CPUs in -march.
f48bdc3... RISC-V: Add autovec mode param.
dcd9d4f... RISC-V: Default-initialize variable.
be1e8ad... RISC-V: Fix some dynamic LMUL costing.
1bb77e9... [RISC-V] Clear both upper and lower bits using 3 shifts
1031246... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
284e3f6... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
92d02da... [RISC-V] Clear high or low bits using shift pairs
ffedbeb... [RISC-V] Improve (x << C1) + C2 split code
6fa2031... [RISC-V][PR target/120368] Fix 32bit shift on rv64
83d1cd5... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
f2827b0... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
2db33cb... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
1ac10ac... [RISC-V] Infrastructure of synthesizing logical AND with co
7f48ec3... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
9b36af9... [PATCH v2 1/2] The following changes enable P8700 processor
808a9f7... [RISC-V] Avoid multiple assignments to output object
3e09287... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
d575be6... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
2737964... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
fd7f4b2... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
0343e16... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
3cd2b66... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
8de7b02... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
288cb4d... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
22c685c... [committed][RISC-V][PR target/120333] Remove bogus bext pat
a73035b... [RISC-V] Fix false positive from Wuninitialized
c90ad16... RISC-V: Fix the warning of temporary object dangling refere
8dff2d8... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
10930f0... RISC-V: Support Zilsd code gen
8c1ecef... RISC-V: Add new operand constraint: cR
7e9043a... [RISC-V] Fix ICE due to bogus use of gen_rtvec
63f3df8... [RISC-V] Avoid setting output object more than once in IOR/
ce6e9b8... RISC-V: Since the loop increment i++ is unreachable, the lo
70bd9f9... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
1e507a8... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
67b5ce2... Make end_sequence return the insn sequence
fa3e7fd... RISC-V: Reuse test name for vx combine test data [NFC]
9bedb72... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
0e93b6b... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
8ca0648... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
b6261f1... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
9965d50... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
ecbcbe8... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
1ef20cc... RISC-V: Adjust vx combine test case to avoid name conflict
83ac2e0... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
a01c446... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
f52b0e9... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
e4a67bf... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
dd3aadb... RISC-V: Add augmented hypervisor series extensions.
2a502c7... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
f49ead4... RISC-V: Regen riscv-ext.opt.urls
fad4fb0... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
0c8209e... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
c4abc6e... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
618045f... RISC-V: Introduce riscv_ext_info_t to hold extension metada
20b9fd0... RISC-V: Adjust riscv_can_inline_p
a84a47c... RISC-V: Generate extension table in documentation from risc
7e49352... RISC-V: Use riscv-ext.def to generate target options and va
e23b0b0... RISC-V: Introduce riscv-ext*.def to define extensions
98baaab... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
3a4090a... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
a3b35d2... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
2fb113c... RISC-V: Support for zilsd and zclsd extensions.
27934c8... testsuite: Fix RISC-V arch-52.c format issue.
adebc28... RISC-V: Support RISC-V Profiles 23.
cf38c7b... RISC-V: Support RISC-V Profiles 20/22.
a4fbb21... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
82c64f7... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
73c5e10... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
db572c6... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
b3dbc5b... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
9a6b9e5... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
fe0c14e... RISC-V: Separate the test running of rvv vx_vf
b805b78... [RISC-V][PR target/120137][PR target/120154] Don't create o
48c19e9... [PATCH] RISC-V: Minimal support for zama16b extension.
781f15e... [RISC-V] Avoid unnecessary andi with -1 argument
e4e2826... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
7ad2997... [PATCH] RISC-V: Recognized svadu and svade extension
a1eefce... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
228476c... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
68684f1... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
327672c... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
0c385d2... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
16bb734... RISC-V: Add gr2vr cost helper function
741d899... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
0f7c778... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
4b02370... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
4a43a8e... [V2][RISC-V] Trivial permutation constant derivation
2556e8d... [RISC-V] Adjust rvv tests after recent jump threading chang
ac8e04a... [PATCH] RISC-V: Implment H modifier for printing the next r
272c570... [to-be-committed][RISC-V] Adjust testcases and finish regis
09b2ff3... RISC-V: Remove unnecessary frm restore volatile define_insn
52306b3... RISC-V: Allow different dynamic floating point mode to be m
954bcab... RISC-V: Fix missing implied Zicsr from Zve32x
4079e20... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
8fab1bb... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
34a7686... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
599b233... RISC-V: Extract vector stepped for expand_const_vector [NFC
33a386d... RISC-V: Extract vector duplicate for expand_const_vector [N
4dbd3df... RISC-V: Extract vec_series for expand_const_vector [NFC]
30644b7... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
94904e5... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
f67aa38... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
885f7fa... [riscv] vec_dup immediate constants in pred_broadcast expan
092714b... [RISC-V][PR target/119865] Don't free ggc allocated memory
1d10214... [RISC-V][PR target/118410] Improve code generation for some
b6f9799... [RISC-V] Fix missed bext discovery
45407ba... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
3e97a50... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
e653247... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
Summary of changes (added commits):
-----------------------------------
5f40721... doc, riscv: Clean up documentation of RISC-V options [PR122
92e7dd6... vect: Make SELECT_VL a convert optab.
81a3128... forwprop: Allow nop conversions for vector constructor.
f5478a8... forwprop: allow subvectors in simplify_vector_constructor (
a3da3e3... forwprop: Check type conversion in pack/unpack [PR123117].
e4b033e... [PR target/121778] Improving rotation detection
86ed53e... [PR123092, LRA]: Reprocess insn after equivalence substitut
c98183b... Fix RISC-V test after recent vectorizer changes
a2eefa8... RISC-V: Enable the ZD constraint only when xmipscbop is ena
f6f71ac... match: Add simplification of `(a*zero_one_valued_p) & b` if
672342e... ifcvt: Improve `cmp?a&b:a` to try with -1 [PR123312]
382dbf9... forwprop: Fix type mismatch in vec constructor [PR123525].
c1d9bcc... if-conv: Prevent vector types in scalar cond reduction [PR1
9499bfc... rtlanal: Determine nonzero bits of popcount from operand [P
e22662d... VN: Fix VN ICE for large _BitInt types
6cf6553... RISC-V: Add support for _BitInt [PR117581]
89e24f2... forwprop: Use ssizetype for mask [PR123414].
a80d633... RISC-V: Update tt-ascalon-d8's extension list [PR123492]
1a4a0c0... ifcvt: Reject inner floating modes of a subreg for noce_try
3d83689... [RISC-V] Clamp long reservations to 7c
3c73ba8... RISC-V: -mrvv-max-lmul=conv-dynamic [PR122846].
3d381dc... [PATCH v3] match.pd: popcount(X & -X) -> -X != 0 [PR102486]
73b3b88... [RISC-V] Restore inline expansion of block moves on RISC-V
5f55eda... [PATCH v1 2/2] RISC-V: Add run test case for vwadd/vwsub wx
b326613... [PATCH v1 1/2] RISC-V: Fix incorrect combine pattern for an
e4f5c93... RISC-V: Adjust the asm check of vx_vf due to middle-end cha
ff5b659... Vect: Adjust depth_limit of vec_slp_has_scalar_use from 2 t
46d3e66... Partially revert patch that made VXRM a global register on
54caf03... [PR target/123010] Simplify shift of sign extracted field t
1359e21... [RISC-V][PR target/121485] Fix mode on Zvkned lmul extendin
8340bd2... [RISC-V][PR target/123318] Use a Pmode temporary for output
d4d592b... ifcvt: Allow non-comparisons against 0 in noce_try_cond_zer
19beb34... ifcvt: Handle lowpart subregs if noce_emit_cmove fails in n
64e358c... ifcvt: cleanup if_info->cond usage in noce_try_cond_zero_ar
6b4af6e... simplify-rtx: Fix up (ne (ior (ne x 0) y) 0) simplification
1b7ccd8... Revert "ifcvt: Move noce_try_cond_zero_arith last"
3c68ef6... [RISC-V][PR target/123283] Wrap naked REG operands with a U
39b1c32... doc: make regenerate-opt-urls
84c5701... doc, riscv: Clean up RISC-V extensions documentation
a78127a... RISC-V: Add test for vec_duplicate + vmsleu.vv combine with
ca0a993... RISC-V: Combine vec_duplicate + vmsleu.vv to vmsleu.vx on G
45f64a7... ifcvt: Move noce_try_cond_zero_arith last
459de01... ifcvt: Only allow scalar integral modes for noce_try_cond_z
5b865a0... [committed][RISC-V][PR target/123274] Add missing condition
704eabc... [RISC-V][PR target/123278] Handle BF/HF modes in Andes 45 s
d289dbd... [RISC-V][PATCH] Adjust clmul latency in Spacemit X60 schedu
8b1fb46... ifcvt: Fix noce_try_cond_zero_arith after get_base_reg chan
3e1d0f3... [RISC-V][V2] Improve spill code for RVV slightly to fix reg
11e3841... ifcvt: cond zero arith: handle subreg for shift count
aa6d5e4... ifcvt: cond zero arith: elide short forward branch for sign
cb4770a... ifcvt: cond zero arith: re-expand output pattern [NFC]
896d600... ifcvt: cond zero arith: factor out common noce_emit_czero e
9af3427... ifcvt: cond zero arith: opencode helper noce_bbs_ok_for_con
7bb2f16... [RISC-V][V2] Improve spill code for RVV slightly to fix reg
ce66f28... RISC-V: Fix overflow check in interleave pattern [PR122970]
ff2f1e2... RISC-V: Testsuite fixes.
572d283... RISC-V: Generic vec_extract via subreg.
d839e61... RISC-V: Add VLS modes to autovec iterators.
2f31ce3... RISC-V: Rename vector-mode related functions.
189894e... RISC-V: Change gather/scatter iterators.
12c0351... Fix various RISC-V testsuite regressions after volatile pat
96311fb... [PATCH] RISC-V: Rename UPPERCAE_NAME to UPPERCASE_NAME
9f56200... RISC-V: Add test for vec_duplicate + vmslt.vv combine with
0d62cd0... RISC-V: Combine vec_duplicate + vmslt.vv to vmslt.vx on GR2
347c220... RISC-V: Regenerate opt urls.
7fceee3... RISC-V: -mmax-vectorization.
7a83aa8... vect: Add vect-scalar-cost-multiplier for SLP.
dbd2fd4... middle-end: Add new parameter to scale scalar loop costing
162cebc... RISC-V: Pragma target [PR115325].
3cd9962... RISC-V: Implement mask reduction.
087111b... [riscv] avoid auipc overflow with large offsets [PR91420]
cef7898... RISC-V: Add test for vec_duplicate + vmsltu.vv combine with
97e663c... RISC-V: Combine vec_duplicate + vmsltu.vv to vmsltu.vx on G
d102971... RISC-V: Remove unused placeholder_p parameter from add_func
1eeff6a... [PATCH][PR target/122942] RISC-V: Add zifencei extension to
1634f44... riscv: RISCV backend, meet C++20
80db728... RISC-V: Emit \n\t at the end of instruction instead of ;
fd2281e... RISC-V: Support --with-cpu
d71ce5e... RISC-V: Add SpacemiT extension xsmtvdot
c73d5fb... RISC-V: Run gen-riscv-ext-opt to regenerate riscv-ext.opt [
3ab7897... RISC-V: Add Andes 45 series pipeline description.
5212b52... RISC-V: Add Andes 23 series pipeline description.
a5a5f1e... RISC-V: Fix one typo result in pr121959-run-1 run failure
a422357... Revert "[PATCH v3] RISC-V: Implement RISC-V profile macro s
dcfc162... RISC-V: Add testcase for unsigned scalar SAT_MUL form 7
0041709... RISC-V: Add BF VLS modes and document iterators.
7db3b88... [PR rtl-optimization/122782] Fix out of range shift causing
1c5e178... [PR 122701] Emit fresh reg->reg copy rather than modifying
841f1ce... [PR118358, LRA]: Decrease pressure after issuing input relo
f085534... RISC-V: Add RTL pass to combine cm.popret with zero return
e968a25... [RISC-V] Fix trivial bootstrap failure on RISC-V
f49b295... RISC-V: Add flag to adjust mem inlining threshold
ee3ca44... [RISC-V] Add cpu and tuning structures for spacemit-x60 des
0e31a81... RISC-V: Remove gather scale and offset handling.
e2959d8... [PR rtl-optimization/122575] Fix mode on optimized IOR comp
5f33452... RISC-V: Add test for vec_duplicate + vmsne.vv combine case
7207ce8... RISC-V: Add test for vec_duplicate + vmsne.vv combine case
f5c4bef... [RISC-V] Avoid most calls to gen_extend_insn
199f9f9... [RISC-V] Drop scan-tests of marginal value
23fc235... RISC-V: Add missing member for andes_25_tune_info
4a270bc... Handle shift-pairs in ext-dce for targets without zero/sign
840a4f2... RISC-V: Add Andes 25 series pipeline description.
f231af9... [RISC-V] Improve detection of packw
013077e... [RISC-V] Simplify riscv_extend_to_xmode_reg
6b0cf05... RISC-V: Add test for vec_duplicate + vmseq.vv combine case
5561f0e... RISC-V: Add test for vec_duplicate + vmseq.vv combine case
1bc9935... [RISC-V] Add testcase for shifted truthvalue
2f17976... RISC-V: Combine vsext.vf2 and vsll.vi to vwsll.vi on ZVBB
383dfe0... RISC-V: Add test for vec_duplicate + vwmaccu.vv combine wit
4bd731c... RISC-V: RISC-V: Combine vec_duplicate + vwmaccu.vv to vwmac
ae25859... [RISC-V] Ignore useless zero-initialization in conditional
d95707e... [RISC-V][PR 121136] Improve various tests which only need t
5107294... RISC-V: testsuite: Fix pr119115.c.
563c0e2... [PR rtl-optimization/122536] Fix guard against variable bit
3ca5bd0... RISC-V: Fix the ABI of empty unions and zero length array i
6bdfb85... [RISC-V][PR tree-optimization/52345] Optimize testing multi
9e2dcc1... [RISC-V] Expose sign extension for 32 bit rotates by consta
f5f8707... gcc: Drop junk vim backup file
05e88f5... [RISC-V][SH][PR rtl-optimization/67731] Improve logical IOR
6c45153... [RISC-V] Reorder ready queue slightly to avoid unnecessary
8771b93... niter: Use ranger to query ctz range.
4b01526... [PATCH v2] RISC-V: avlprop: Scale AVL by subreg ratio [PR12
5f5d359... RISC-V: Clean up build warnings for VLS calling convention
e424d12... Skip riscv/rvv/xtheadvector/pr116593.C if not hostedlib
56d89a6... RISC-V: Add testsuite for fixed-length vector calling conve
5242b85... RISC-V: Add testsuite for fixed-length vector calling conve
5db7db2... RISC-V: Implement standard fixed-length vector calling conv
686be7a... [RISC-V][PR target/64345][PR tree-optimization/80770] Impro
5c02a3b... Increase NUM_ABI_IDS to support RISC-V VLS calling conventi
2601481... [PATCH v2] RISC-V: Fix moving data from V_REGS to GR_REGS b
16c6951... Fix minor RISC-V testsuite failure
8382236... Fix minor testsuite scan failures for RISC-V
5fc8a8b... RISC-V: Add testcase for unsigned scalar SAT_MUL form 6
95f0067... RISC-V: Fix incorrect op of vwaddu/vwsubu wx combine
b40bb5c... [PATCH v3] RISC-V: Implement RISC-V profile macro support
f466b3f... [RISC-V][PR target/120811] Improving address reloads in LRA
235f02f... [PR target/119587] RISC-V: xtheadmemidx: Split slli.uw patt
6560d2f... [RISC-V] Improve subword atomic patterns in sync.md
98eb1f0... RISC-V: Add test for vec_duplicate + vwsubu.wv combine with
839cf9d... RISC-V: Combine vec_duplicate + vwsubu.wv to vwsubu.wx on G
c1d646c... RISC-V: Allow VLS types using up to LMUL 8
5f0fa69... [PATCH] RISC-V: Fix slide pattern recognition [PR122124]
164a09e... RISC-V: Combine vec_duplicate + vwaddu.wv to vwaddu.wx on G
0e3e5fa... ISC-V: Add test for vec_duplicate + vwaddu.wv signed combin
2ba8720... Fixup merge conflict
954bb2f... [PATCH v2] RISC-V: Fix type of CFA during stack probe [PR12
5d01786... [RISC-V][PR target/122147] Avoid creating (subreg (mem)) in
fdcb73f... [PR target/118945][PATCH v3] RISC-V: Add 'prefer_agnostic'
bc6c445... [RISC-V][PR rtl-optimization/121937] Don't call neg_poly_in
89dd103... [RISC-V][PR target/122051] Fix pmode_reg_or_uimm5_operand f
c9bb431... [RISC-V][PR target/122106] Add missing predicate on crc exp
a062e47... [PATCH][PR target/121778] RISC-V: Improve rotation detectio
a6406a6... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
027ffa6... RISC-V: Add missing define_insn_reservation to tt-ascalon-d
8270e39... [RISC-V][PR target/121983] Fix unprotected REGNO invocation
507d4b2... RISC-V: Improve slide patterns recognition
0460652... RISC-V: Only Save/Restore required registers for ILP32E/LP6
959cb14... [RISC-V] Optimize clear-lowest-set-bit sequence when ctz is
fb35a01... RISC-V: Correct lmul estimation
6a09fd2... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
1ac9437... [PR tree-optimization/58727] Don't over-simplify constants`
b26c9ab... RISC-V: Add test for vec_duplicate + vwmulu.vv signed combi
8de41a0... RISC-V: Add test for vec_duplicate + vwsubu.vv signed combi
e4ad81d... RISC-V: Add test for vec_duplicate + vwaddu.vv signed combi
bf3d8fd... RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on G
e99a63c... RISC-V: Allow profiles input in '--with-arch' option.
9b804d8... RISC-V: Configure Profiles definitions in the definition fi
26586fd... RISC-V: Imply zicsr for sdtrig and ssstrict extensions.
251f1f9... Widening-Mul: Refine build_and_insert_cast when rhs is cast
c3c8ae3... RISC-V: Fix vendor intrinsic tests for disabled multilib co
9808669... RISC-V: Support vnclip idiom testcase [PR120378]
be747da... Match: Support SAT_TRUNC variant NARROW_CLIP
3ee81d1... [RISC-V] Adjust ABI specification in recently added Andes t
d52f37d... RISC-V: Suppress cross CC sibcall optimization from vector
4007f26... RISC-V: Add min/max patterns for ifcvt.
401b0f2... ifcvt: Clarify if_info.original_cost.
5986829... RISC-V: Fix can_find_related_mode_p for VLS types
b135a22... RISC-V: Fix typo in tt-ascalon-d8's pipeline description [P
e0d2ffe... RISC-V: Add pattern for vector-scalar single widening float
284806c... RISC-V: Add pattern for vector-scalar dual widening floatin
49c1186... RISC-V: Add pattern for vector-scalar single widening float
81405ea... RISC-V: Add pattern for vector-scalar widening floating-poi
a23e0cd... RISC-V: Adjust tt-ascalon-d8 branch cost
9b07b82... RISC-V: Add pattern for vector-scalar single-width floating
030454f... RISC-V: Add pattern for vector-scalar single-width floating
ca083a4... RISC-V: Add pattern for vector-scalar single-width floating
eb1c109... RISC-V: Add pattern for vector-scalar widening floating-poi
264cbce... RISC-V: Add patterns for vector-scalar IEEE floating-point
ecc9920... gcc: introduce the dep_fusion pass
c2a5758... RISC-V: Add support for the XAndesvdot ISA extension.
e1dc28f... [RISC-V] Fix ordering of pipeline models
15c0132... RISC-V: Add support for the XAndesvpackfph ISA extension.
4ec4509... RISC-V: Add test for vec_duplicate + vnmsub.vv unsigned com
522fbd4... RISC-V: Add test for vec_duplicate + vnmsub.vv signed combi
f41e005... RISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub.vx on G
be5a4e7... dep_fusion: Fix if target does not have macro fusion [PR121
753616e... gcc: introduce the dep_fusion pass
fe622bb... RISC-V: Add support for the XAndesvsintload ISA extension.
0116cf6... RISC-V: Add support for the XAndesvbfhcvt ISA extension.
b35dca4... RISC-V: Add tt-ascalon-d8 pipeline description
fe7036a... [RISC-V] Adjust recently added test
49e97f1... RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2
b6f95a8... RISC-V: Allow errors to be suppressed when parsing architec
002fb3b... RISC-V: Adjust the vmacc.vx combine test cases
535a8d4... RISC-V: Add test for vec_duplicate + vmadd.vv unsigned comb
37565a1... RISC-V: Add test for vec_duplicate + vmadd.vv signed combin
b02e602... RISC-V: Fix extension subset check in riscv_can_inline_p
ff4fbd9... RISC-V: Add support for the XAndesbfhcvt ISA extension.
91df4d6... RISC-V: Add support for the XAndesperf ISA extension.
f7c5d8a... RISC-V: Add basic XAndes vendor extension support.
86f3add... RISC-V: Add pattern for vector-scalar floating-point max
2acdf01... [RISC-V][PR target/121213] Avoid unnecessary sign extension
6bf2209... RISC-V: Fix is_vlmax_len_p and use for strided ops.
8fa31a6... RISC-V: Add Zbb extension sext testcase.
54ba891... RISC-V: Update Zba 'shNadd.uw' testcase.`
9f4235f... RISC-V: Remove unused print_ext_doc_entry function [NFC]
a4d76a3... [RISC-V] Improve initial RTL generation for SImode adds on
ba3290f... RISC-V: Add test case for unsigned scalar SAT_MUL form 4
68eb204... RISC-V: Add patterns for vector-scalar IEEE floating-point
21651cb... RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned com
5117bea... RISC-V: Add test for vec_duplicate + vnmsac.vv signed combi
3ce218d... RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on G
db02e92... RISC-V: Add pattern for vector-scalar floating-point min
c8f7455... Remove xfail marker on RISC-V test
5dba2c9... RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv
184a0f0... More RISC-V testsuite hygiene
5ce1607... [committed] RISC-V Testsuite hygiene
03f89fc... [PATCH] RISC-V: Add pattern for reverse floating-point divi
136e651... [PATCH] RISC-V: Add pattern for vector-scalar single-width
8c35dda... Fix RISC-V bootstrap
31ddf2f... RISC-V: Add test for vec_duplicate + vmacc.vv unsigned comb
e2d6eb6... RISC-V: Add test for vec_duplicate + vmacc.vv signed combin
ba7b5c1... RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2
b6b08f6... RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE mac
575b89e... Fix invalid right shift count with recent ifcvt changes
a6bf8bf... [PR rtl-optimization/120553] Improve selecting between cons
46c6ad2... RISC-V: Add testcase for scalar unsigned SAT_MUL form 3
a19eae2... RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh
a7a6efe... [PR target/121213] Avoid unnecessary constant load in amosw
357b90b... regrename: treat writes as reads for fused instruction pair
c1129dc... ira: tie output allocnos for fused instruction pairs
6697f4c... [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR
e6d6f64... RISC-V: Update the comments of vx combine [NFC]
da9f5fe... RISC-V: Add missed DONE for vx combine pattern [NFC]
e8bb381... RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and ca
ee98f61... [PR target/119275][RISC-V] Avoid calling gen_lowpart in cas
85e9eb2... [RISC-V][PR target/121531] Cover missing insn types in p400
f94e018... [RISC-V][PR target/121160] Avoid bogus force_reg call
ec46f42... [RISC-V][PR target/121113] Handle HFmode in various insn re
1447123... RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm com
dbe8497... RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on G
3e5fa7e... RISC-V: Expand const_vector with 2 elts per pattern.
14f89fa... Improve initial code generation for addsi/adddi
ca31f45... Don't run tests requiring "B" on designs without "B"
fbbe2dd... RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
52be934... RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost
8062a51... RISC-V: Read extension data from riscv-ext*.def for arch-ca
16488bd... RISC-V: Support -march=unset
b1d4b7b... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
57d72fd... RISC-V: Add testcases for signed avg ceil vx combine
f4bd0c9... RISC-V: Adding H to the canonical order [PR121312]
1673475... RISC-V: Add testcases for unsigned avg ceil vx combine.
78442e9... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
62294f9... RISC-V: Remove use of structured binding to fix compiler wa
9d85b1e... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
9262657... RISC-V: Add test case for vaadd.vx combine polluting VXRM
d38a311... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
cf0277c... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
f9c27d4... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
c289ebe... RISC-V: Fix another vf FP16 combine run test failures
0d7ac2c... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
cf2129a... RISC-V: Prepare dynamic LMUL heuristic for SLP.
72543a1... RISC-V: Remove user-level interrupts
8f6f168... RISC-V: Add support for resumable non-maskable interrupt (R
c9eaaa6... riscv: testsuite: Fix misalignment check.
1a0cf11... RISC-V: Add test case for vx combine polluting VXRM
dd431ba... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
6a7bc07... RISC-V: Rework broadcast handling [PR121073].
239c4eb... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
003ac21... Change bellow in comments to below
dcb469c... [RISC-V] Restrict generic-vector-ooo DFA
5d48b1b... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
0088eef... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
c0e5a77... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
23e9bbb... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
da9aa51... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
9599d12... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
223df03... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
1be9436... RISC-V: Refine the test case for vector avg_floor and avg_c
52d14ed... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
be3d9c7... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
3ff05cc... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
02d96a4... RISC-V: Support RVVDImode for avg3_ceil auto vect
cf6c319... RISC-V: Fix vsetvl merge rule.
14c584d... RISC-V: Refine the scalar SAT_* test cases
7ed225c... RISC-V: Support RVVDImode for avg3_floor auto vect
c951d23... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
4077a4f... RISC-V: Add testcase for rv32 SAT_MUL from uint64
f92f580... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
37d07d1... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
60e9d7a... RISC-V: Make zero-stride load broadcast a tunable.
162fa5c... [RISC-V] Detect new fusions for RISC-V
5714040... RISCV: Remove the v extension requirement for sat scalar ru
61f7b6a... RISC-V: Add test for vec_duplicate + vssub.vv combine case
fe51701... RISC-V: Add test for vec_duplicate + vssub.vv combine case
a59c3a6... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
83f7bd9... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
eceb939... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
b2d6f7a... [RISC-V][PR target/120642] Avoid propagating constant AVL f
81f669b... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
c002455... RISC-V: Do not use vsetivli for THeadVector.
aa43dac... RISC-V: Ignore non-types in builtin function hash.
53d96ba... [committed][RISC-V] Fix testsuite fallout from check-functi
953f418... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
27d0274... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
3a1b3d4... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
5082e58... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
756881a... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
e2e337c... [RISC-V] Add basic instrumentation to fusion detection
724ea37... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
bec3307... Refactor record_function_versions.
ff7c2c9... [RISC-V][PR target/118886] Refine when two insns are signal
3426d7d... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
b1f931a... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
3dddca5... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
6b87b22... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
4149b5d... RISC-V: Reconcile the existing test due to cost model chang
400c15a... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
47bea53... RISC-V: Ignore -Oz for most rvv testcase [NFC]
c8933cb... RISC-V: Primary vector pipeline model for sifive 7 series
4383c1f... RISC-V: Adding B ext, fp16 and missing scalar instruction t
85f2082... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
32e1d40... RISC-V: Refactor the function bitmap_union_of_preds_with_en
24850c0... RISC-V: Add pipeline-checker script
0922b63... [RISC-V][PR target/119971] Avoid losing shift count masking
c234680... RISC-V: update prepare_ternary_operands to handle vector-sc
e37d44f... RISC-V: Fix build issue
1c07217... RISC-V: Add comment and reorder the the include files in ri
c73cb8a... RISC-V: Add Profiles RVA/B23S64 support.
ae9b218... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
0745a00... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
2fa0144... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
9a15d12... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
db8e41d... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
d8b9853... RISC-V: Fix ICE for expand_select_vldi [PR120652]
c0a02d4... [RISC-V] Force several tests to use rocket tuning
a389820... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
c40d74b... RISC-V: Add test for vec_duplicate + vminu.vv combine case
1ef09d0... RISC-V: Add test for vec_duplicate + vminu.vv combine case
75c16b9... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
25ea4cf... RISC-V: Add generic tune as default.
184b97d... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
f82585e... RISC-V: Adding cost model for zilsd
4db441a... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
0068288... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
c7ce525... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
56f7ca8... [PATCH v1] RISC-V: Use scratch reg for loop control
2fc718e... RISC-V: Add -fno-pie flags to testcases
720de21... RISC-V: Refine VX combine test case 0 to avoid code duplica
911d1b1... RISC-V: Update Profiles string in RV23.
e10112b... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
1aed36e... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
f539a6f... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
11cbbb8... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
6e408d9... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
f369f19... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
3164d56... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
5830499... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
f0195f2... RISC-V: Prevent speculative vsetvl insn scheduling
97c34ce... RISC-V: Add patterns for vector-scalar negate-(multiply-add
9070724... RISC-V: testsuite: fix an obvious build error
c9bad40... RISC-V: Regen riscv-ext.texi [NFC]
3117ff8... RISC-V: Add test for vec_duplicate + vremu.vv combine case
b08b9e3... RISC-V: Add test for vec_duplicate + vremu.vv combine case
8b0489e... RISC-V: Reconcile the existing test for vremu.vx combine
b55e9a2... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
e3c45b9... [RISC-V] Enable more if-conversion on RISC-V
32faf90... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
81bebaf... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
c833dbc... RISC-V: Reconcile the existing test for vrem.vx combine
c93bc00... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
e0469f1... RISC-V: frm/mode-switch: robustify call_insn backtracking [
8939615... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
84ddf63... RISC-V: frm/mode-switch: remove dubious frm edge insertion
3442314... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
938afe9... [RISC-V] Handle 32bit operands in condition for conditional
9304697... [to-be-committed][RISC-V] Handle 32bit operands in conditio
503c73b... RISC-V: Reconcile the existing test for vdivu.vx combine
a768b6f... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
322e8b4... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
3e7db29... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
982fad6... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
60ee05d... [RISC-V] Improve signed division by 2^n
7dd5b77... RISC-V: Don't use structured binding in riscv-common.cc
7625380... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
b2889cf... [RISC-V] Improve sequences to generate -1, 1 in some cases.
7f2e263... RISC-V: Support Ssu64xl extension.
3020174... RISC-V: Support Sstvecd extension.
c15b3c1... RISC-V: Support Sstvala extension.
f028b49... RISC-V: Support Sscounterenw extension.
880e9dc... RISC-V: Support Ssccptr extension.
de642fe... RISC-V: Support Smrnmi extension.
01fea86... RISC-V: Support Sm/scsrind extensions.
d9a1933... RISC-V: Update extension defination.
2e83517... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
628e3ac... [PATCH v2] RISC-V: Add svbare extension.
a36e2ca... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
258a7a9... RISC-V: Add Shlcofideleg extension.
6c233df... RISC-V: Reconcile the existing test for vdiv.vx combine
8d14b6c... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
98f1332... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
a142182... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
aee9cdd... RISC-V: Use helper function to get FPR to VR move cost
cf38773... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
ded810d... [PATCH] RISC-V: Add smcntrpmf extension.
7244f8f... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
be260da... RISC-V: Implement full-featured iterator for riscv_subset_l
a8ec06c... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
b4f3d0e... RISC-V: Fix line too long format issue for autovect.md [NFC
bc19900... RISC-V: Add test cases for avg_ceil vaadd implementation
1bb6166... RISC-V: Reconcile the existing test for avg_ceil
dba586a... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
26f85a8... RISC-V: Add minimal support of double trap extension 1.0
5be4801... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
d384abf... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
f7cabe8... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
08a76e6... RISC-V: Avoid division by zero in check_builtin_call [PR120
1fdbc4c... RISC-V: Add test cases for avg_floor vaadd implementation
257289e... RISC-V: Reconcile the existing test for avg_floor
70e894e... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
f097cdb... [RISC-V] Add andi+bclr synthesis
e9ff3ab... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
dec63a8... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
8a8dc0b... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
01d86ed... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
d6e01fa... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
edc2eca... [RISC-V] shift+and+shift for logical and synthesis
88efeee... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
eefcfe5... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
7b1c295... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
7288754... RISC-V: Support CPUs in -march.
dcc501f... RISC-V: Add autovec mode param.
43162a4... RISC-V: Default-initialize variable.
20b4617... RISC-V: Fix some dynamic LMUL costing.
12a0ffa... [RISC-V] Clear both upper and lower bits using 3 shifts
c9f2fca... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
1977f8b... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
87d05fe... [RISC-V] Clear high or low bits using shift pairs
a5445e4... [RISC-V] Improve (x << C1) + C2 split code
787e396... [RISC-V][PR target/120368] Fix 32bit shift on rv64
587fcc2... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
93c36d2... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
5e47970... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
701ba62... [RISC-V] Infrastructure of synthesizing logical AND with co
b0bcb4e... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
9d42146... [PATCH v2 1/2] The following changes enable P8700 processor
327a4cf... [RISC-V] Avoid multiple assignments to output object
38f7ba9... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
f954c16... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
87fb9af... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
0e1cfc7... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
ed70e05... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
a9a1017... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
72a13e0... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
311c474... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
f907040... [committed][RISC-V][PR target/120333] Remove bogus bext pat
3fb8293... [RISC-V] Fix false positive from Wuninitialized
a130d20... RISC-V: Fix the warning of temporary object dangling refere
8381ff3... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
5e3190e... RISC-V: Support Zilsd code gen
e27f8f8... RISC-V: Add new operand constraint: cR
9d9740a... [RISC-V] Fix ICE due to bogus use of gen_rtvec
e9be6f2... [RISC-V] Avoid setting output object more than once in IOR/
c4a8a1f... RISC-V: Since the loop increment i++ is unreachable, the lo
56d4d5c... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
aa98292... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
054b1d0... Make end_sequence return the insn sequence
ba3ec40... RISC-V: Reuse test name for vx combine test data [NFC]
d017da4... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
4aab909... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
26057c0... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
5d2571a... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
c2873e8... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
da2c054... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
e13a035... RISC-V: Adjust vx combine test case to avoid name conflict
f497f30... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
23ae176... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
d9d2650... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
5fbbe8e... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
3723b04... RISC-V: Add augmented hypervisor series extensions.
2054408... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
fbac98a... RISC-V: Regen riscv-ext.opt.urls
c6c59ba... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
4c85846... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
84d1d70... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
a5141fc... RISC-V: Introduce riscv_ext_info_t to hold extension metada
ae18da5... RISC-V: Adjust riscv_can_inline_p
d656879... RISC-V: Generate extension table in documentation from risc
af7d498... RISC-V: Use riscv-ext.def to generate target options and va
a2495b8... RISC-V: Introduce riscv-ext*.def to define extensions
4b8425a... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
317b87a... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
324b7ce... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
96b6084... RISC-V: Support for zilsd and zclsd extensions.
cfb4064... testsuite: Fix RISC-V arch-52.c format issue.
ee21d98... RISC-V: Support RISC-V Profiles 23.
1fc5c6e... RISC-V: Support RISC-V Profiles 20/22.
963905f... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
db6cefb... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
d653b0d... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
4254554... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
8f0927d... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
f9cb05e... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
5ac60df... RISC-V: Separate the test running of rvv vx_vf
8bff3e3... [RISC-V][PR target/120137][PR target/120154] Don't create o
0ee3378... [PATCH] RISC-V: Minimal support for zama16b extension.
4d120bb... [RISC-V] Avoid unnecessary andi with -1 argument
a71e279... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
742ce46... [PATCH] RISC-V: Recognized svadu and svade extension
faf7f8b... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
aa7ff63... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
a9df266... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
7855267... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
be40a5a... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
3b95719... RISC-V: Add gr2vr cost helper function
78976e4... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
f420f1e... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
c932d73... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
8d39353... [V2][RISC-V] Trivial permutation constant derivation
2cf6ccf... [RISC-V] Adjust rvv tests after recent jump threading chang
1f43143... [PATCH] RISC-V: Implment H modifier for printing the next r
bf2957e... [to-be-committed][RISC-V] Adjust testcases and finish regis
a3e05b6... RISC-V: Remove unnecessary frm restore volatile define_insn
1c071ee... RISC-V: Allow different dynamic floating point mode to be m
b17b29f... RISC-V: Fix missing implied Zicsr from Zve32x
267b826... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
2b1a22e... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
6627ec0... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
4519ab1... RISC-V: Extract vector stepped for expand_const_vector [NFC
98b4405... RISC-V: Extract vector duplicate for expand_const_vector [N
e33c2ec... RISC-V: Extract vec_series for expand_const_vector [NFC]
7bb01d0... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
eca9631... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
3428a2b... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
3a1daa0... [riscv] vec_dup immediate constants in pred_broadcast expan
208c0d6... [RISC-V][PR target/119865] Don't free ggc allocated memory
52c6cb8... [RISC-V][PR target/118410] Improve code generation for some
3d9fe66... [RISC-V] Fix missed bext discovery
a0e1b6f... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
d6a0e77... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
233fc87... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
11a031a... Daily bump. (*)
1c2461e... i386: Fix up movhf_mask constraints [PR123607] (*)
10c9209... combine: Partially revert the r12-4475 changes [PR120250] (*)
c5801ea... simplify-rtx: Fix up shift/rotate VOIDmode count handling [ (*)
bacfbe0... ranger: Verify gimple_call_num_args for several builtins [P (*)
e08a60b... doc: List more valid -x option arguments (*)
4c662fc... i386: Add OPTION_MASK_ISA_64BIT to 4 non-ia32 builtins [PR1 (*)
12c0f78... stmt: Fix up parse_input_constraint [PR111817] (*)
fc38841... combine: Fix up serious regression in try_combine [PR121773 (*)
7debee2... tree-object-size: Deterministic SSA generation [PR123351] (*)
5d343a4... widening_mul: Fix up .SAT_{ADD,SUB,MUL} pattern recognition (*)
5a2e515... c++: Fix error recovery for invalid arrays [PR123331] (*)
a495ca6... i386: Fix up expansion of 2 keylocker and one user_msr buil (*)
cc4cf78... c++: Suppress -Wreturn-type warnings for functions with fai (*)
66d1adb... c++: Fix stabilization of bitfields [PR122772] (*)
01f6bee... ++: Fix up cp_compare_floating_point_conversion_ranks for d (*)
354cad7... docs: Fix up typo in --with-tls= description (*)
70bea73... i386: Obfuscate _mm_maskmove_si64 local variable [PR123155] (*)
89b4304... i386: Obfuscate avx10_2bf16intrin.h inline function argumen (*)
d4978c4... aarch64: Accept hyphenated extensions in --with-arch [PR123 (*)
ac40092... [PR123121, LRA]: Fix wrong rematerialization of insns with (*)
062b2df... expand: Handle variable-length vector constructors with deb (*)
c3e9375... LoongArch: Fix bug123521. (*)
4854414... Daily bump. (*)
e547218... LoongArch: Fix ICE when explicit-relocs is none (*)
1877040... Daily bump. (*)
004e2f3... analyzer: fix strlen(STRING_CST + OFFSET) [PR123085] (*)
e869244... analyzer: fold X + (-X) to zero [PR122975] (*)
e2b6c1c... c++: fix count of z candidates for non-viable candidates, n (*)
2fdebdd... diagnostics: handle fatal_error in SARIF output [PR120063] (*)
5bb0345... testsuite: fix typo in name of plugin test file (*)
e8238de... git_commit.py: add "diagnostics" to bug components (*)
deffc35... Daily bump. (*)
57305e1... Early builtin_unreachable removal must examine dependencies (*)
90c718d... Add TARGET_MMX_WITH_SSE to the condition of all 64-bit _Flo (*)
0139109... Daily bump. (*)
8807594... Daily bump. (*)
9f22bf9... Daily bump. (*)
1abc44f... Daily bump. (*)
50a3d36... testsuite/123353 - require little-endian for testcase (*)
05f0bab... c/123156 - overflow in shuffle mask for __builtin_shuffleve (*)
eeb6091... tree-optimization/123040 - handle nary -> ifn simplificatio (*)
66fe4ac... c++: Allow lambda expressions in template type parameters [ (*)
1e9e8c3... c++: implicit 'this' in generic lambda [PR122048] (*)
0836fd4... c++: xobj lambda ICE [PR121854] (*)
1648ce0... Daily bump. (*)
a5d1011... Daily bump. (*)
a45e792... Fix gcc.c-torture/execute/pr110817-[13].c on the SPARC (*)
5bf4cb9... Daily bump. (*)
ec58ebc... Update cpplib ka.po (*)
af37897... Daily bump. (*)
5942d9f... Daily bump. (*)
6a64f6c... Ada: Fix infinite loop on iterated element association with (*)
7765c0c... Daily bump. (*)
a75d15d... [RISC-V][PR target/121485] Fix mode on Zvkned lmul extendin (*)
5fe0ba5... Daily bump. (*)
5944c77... Daily bump. (*)
e8780f3... Daily bump. (*)
a54c5e2... Daily bump. (*)
80a4162... Daily bump. (*)
0396faa... Daily bump. (*)
7f67208... Ada: Fix assertion failure for unfrozen mutably tagged type (*)
3c792b6... Daily bump. (*)
6f1232d... Ada: Adjust fix for internal error on illegal aggregate for (*)
f3ab0ca... Ada: Fix bogus error on aggregate in call with qualified ty (*)
f6ecd72... Ada: Fix illegal Aggregate aspect not rejected (*)
1982bfa... Daily bump. (*)
1d26b1b... Ada: Fix bogus component visibility error for class-wide ty (*)
c85e42d... Daily bump. (*)
c5117c4... Daily bump. (*)
d7f993b... c++/modules: Reattempt to complete ARRAY_TYPEs after readin (*)
b47a00a... Daily bump. (*)
7945fa5... Ada: Fix ICE in fld_incomplete_type_of when building GtkAda (*)
0ee13aa... Ada: Fix ICE in fld_incomplete_type_of when building GtkAda (*)
1f158f0... vect: don't hoist conditional loads above their condition [ (*)
413fa36... Daily bump. (*)
216c4be... Fortran: Fix bad read involving extra input text. (*)
5ab82f2... Daily bump. (*)
89a05e9... Daily bump. (*)
ba39d22... dwarf: Save bit stride information for array type entry [PR (*)
4740853... Fix comment for VECTOR_BOOL_MODE (*)
924d7a7... Daily bump. (*)
0c10490... Daily bump. (*)
f1d72ba... libstdc++: Update tzdata to 2025c (*)
e7664c0... libstdc++: Do not optimize std::copy to memcpy for bool out (*)
48f85d3... libstdc++: std::atomic should use std::addressof (*)
a4921df... libstdc++: Fix pretty printer lookup for class templates [P (*)
83020b9... libstdc++: Fix nodiscard warnings in performance tests (*)
88c8959... Daily bump. (*)
bb061a3... c++: nested typename type resolving to wildcard type [PR122 (*)
151c383... libstdc++: Implement P2655R3 changes to common_reference bu (*)
95f5abd... libstdc++: Consolidate bullet 1 __common_reference_impl par (*)
44eb671... c++: current inst name lookup within noexcept-spec [PR12266 (*)
d7f9edb... RISC-V: Add more mode_idx attributes [PR123022]. (*)
0f800bb... Fortran: Fix wrongly rejected allocatable LOCK_TYPE [PR1074 (*)
d01bb00... Daily bump. (*)
043ed7e... Ada: Fix ICE when comparing reduction expression with integ (*)
2171c34... Ada: Fix ICE in fld_incomplete_type_of when building GtkAda (*)
9c40962... Daily bump. (*)
9bac272... Daily bump. (*)
d3dd4de... Daily bump. (*)
01cb1fd... Daily bump. (*)
d2136fa... Ada: Fix internal error on incomplete private tagged type (*)
8bc11df... [PR122215, IRA]: Fix undefined behaviour of improve_allocat (*)
d0d04df... [PATCH] libgomp: Fix GCC build after glibc@cd748a6 (*)
968e9b3... Ada: Fix internal error on illegal aggregate for private ty (*)
1b6bc90... c: Reject vector type bit-fields [PR123018] (*)
e2cee39... Daily bump. (*)
014dd4b... RISC-V: vsetvl: Add null check for fault-first loop [PR1226 (*)
dafaf53... Daily bump. (*)
7978efd... Fortran: associate to a contiguous pointer or target [PR122 (*)
4028e6c... [PATCH] RISC-V: Make vlsegff similar to vleff [PR122656]. (*)
394fe8e... Daily bump. (*)
e51d958... Ada: Add missing #include for MinGW (*)
1093213... aarch64: Fix crc{,_rev}<SWI124:mode>si4 expanders [PR122991 (*)
d6b210b... i386: Fix crc_rev<SWI124:mode>si4 expander [PR122991] (*)
9c049f4... switchconv: Fix up inbound checks for switch types wider th (*)
f4d19f7... c: Fix ICE in c_type_tag on va_list [PR121506] (*)
e7399b9... gimplify, ubsan: Fix -fopenmp -fsanitize=bounds ICE [PR1200 (*)
b9693df... openmp: Fix up OpenMP expansion of collapsed loops [PR12056 (*)
a4d2248... alias: Fix up BITINT_TYPE and non-standard INTEGER_TYPE ali (*)
1f0224e... libcody: Make it buildable by C++11 to C++26 (*)
5ef6443... c++: Fix up build_data_member_initialization [PR121445] (*)
1788588... c++: Fix error recovery ICE in tsubst_baselink [PR120876] (*)
2e803b4... Daily bump. (*)
d7964e8... Daily bump. (*)
082f983... Ada, Darwin: Implement OSLock for Darwin [PR115305]. (*)
1771473... Daily bump. (*)
c48fa78... Daily bump. (*)
abe3c7e... Daily bump. (*)
b0e3253... lto/122515: Avoid using SSIZE_MAX (*)
254c870... Daily bump. (*)
29ef8ea... Daily bump. (*)
0a52c19... libstdc++: Inconsistent const in flat_map's value_type [PR1 (*)
4d8f72b... arm: Fix constraints in MVE asrl and lsll patterns [PR12285 (*)
746e09b... arm: Only reverse FP inequalities when -ffinite-math-only [ (*)
3cadc19... Daily bump. (*)
043c5c4... Daily bump. (*)
26dcd23... Daily bump. (*)
236279e... libstdc++: Correctly implement LWG 3946 changes to const_it (*)
43f60f5... c++: fix ICE with consteval functions in template decls [PR (*)
481c3ec... isel: Check bounds before converting VIEW_CONVERT to VEC_SE (*)
0147bd0... Daily bump. (*)
b1b7cc0... AVR: Add new devices AVR16LA14/20/28/32 and AVR32LA14/20/28 (*)
fc0d96c... arm: handle long-range CBZ/CBNZ patterns [PR122867] (*)
0faf04d... Daily bump. (*)
3945c6b... c++: fix crash with pack indexing in noexcept [PR121325] (*)
fa27ae2... Daily bump. (*)
dabaca8... c++/modules: Stream all REQUIRES_EXPR_PARMS [PR122789] (*)
c69799f... arm: add extra sizes to Wstrinop-overflow-47.c warning test (*)
832f476... Daily bump. (*)
6b368b8... [PATCH v1] RISC-V: Fix missed zero extend for unsigned scal (*)
2481b8b... Daily bump. (*)
b34f570... Daily bump. (*)
de19b86... Daily bump. (*)
f08ceb5... Aarch64: Fix pasto in user manual (*)
76e9b0d... ada: Remove suspicious entries generated by -gnatR for gene (*)
d4a8b3d... ada: Fix small typo in comment (*)
31ed7ae... ada: Fix bogus error about null exclusion for designated ty (*)
be07701... c++: make __reference_*_from_temporary honor access [PR1205 (*)
40f744f... Daily bump. (*)
36dd19f... tree-optimization/122225 - fix return stmt verification (*)
413668c... [i386] Fix type in ix86_move_max setup (*)
9c92b2b... LoongArch: Fix wrong code from loongarch_expand_vec_perm_1 (*)
678cfb3... Daily bump. (*)
4da6e03... libstdc++: Update GCC 15.1 library versions in docs [PR1227 (*)
41b54f4... libstdc++: Remove vertical whitespace from code listings in (*)
66ead3e... c++: fix ICE when comparing targs [PR119580] (*)
ed2f88d... Daily bump. (*)
60db9b6... Fortran: contiguous pointer assignment to select type targe (*)
bad5acb... c++: Handle absolute path for CMI output directory [PR12267 (*)
24f252c... arm: Fix out of bounds when using cmse with FP types in agg (*)
0ea9ba6... arm: Fix CMSE clearing of union members with no padding [PR (*)
9fa75e4... lto/122515: Fix archive offset types for i686 (*)
d207ebc... libstdc++: Fix error reporting for filesystem::rename on Wi (*)
a4ee0e3... AArch64: support bf16 to sf extensions [PR121853] (*)
21866f2... strlen: Fixup load alignment for memcmp (*)
f30c88d... Daily bump. (*)
5f28f7c... docs: Fix __builtin_object_size example [PR121581] (*)
e463218... libstdc++: Fix std module for gcc4-compatible ABI (*)
dfe60ee... [RISC-V][PR rtl-optimization/122627] Yet another fix in IRA (*)
833a744... Daily bump. (*)
8fc013b... c++/modules: Keep tracking instantiations of static class v (*)
ba342ff... diagnostics: Fix -fdump-internal-locations for 64-bit locat (*)
d7af574... Daily bump. (*)
184a135... Daily bump. (*)
e4f4921... [PR target/119275][RISC-V] Avoid calling gen_lowpart in cas (*)
3bc54cf... i386: Remove 'i' from output operand constraint (*)
2e9bed7... libstdc++: Fix std::forward_list::assign assignable check [ (*)
6cd6125... arm: [MVE intrinsics] rework asrl lsll [PR122216] (*)
69bd3cb... arm: [MVE intrinsics] add scalar_s64_shift scalar_u64_shift (*)
33f30a7... arm: add support for out of range shift amount in MVE asrl (*)
d1ba5b1... arm: fix MVE asrl lsll lsrl patterns [PR122216] (*)
5c3d1bf... Daily bump. (*)
b4a55fe... Daily bump. (*)
42a9b43... testsuite: arm: mve: Adjust testcases [PR122175] (*)
907895c... arm: mve: avoid invalid immediate values in vbicq_n, vorrq_ (*)
a48912e... arm: [MVE] Fix carry-in support for vadcq / vsbcq [PR122189 (*)
f243074... Ada: Fix variable initialized with if-expression not flagge (*)
5fac2f4... ada: Set Ekind early in object declarations (*)
594f4fb... i386: Support C++ template parameters in AMX intrinsics [PR (*)
afcc1a8... Daily bump. (*)
2e22ffe... gimplify-me: Fix regimplification of gimple-reg-type clobbe (*)
1352498... LoongArch: Fix PR122097 (2). (*)
08be034... LoongArch: Fix bug for PR122097. (*)
ee46a13... LoongArch: Move vector templates of and xor ior to simd.md. (*)
ac34de5... Daily bump. (*)
c2f7c3f... Update gcc es.po (*)
22dd50d... arm: Don't reject early mov?fcc patterns that we might be a (*)
545bdfc... arm: avoid unmatched insn in movhfcc [PR118460] (*)
ef71446... Daily bump. (*)
2e45818... Daily bump. (*)
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