https://gcc.gnu.org/g:501baaf50c72a684000b077413e19635df598a86
commit r16-6922-g501baaf50c72a684000b077413e19635df598a86 Author: Kyrylo Tkachov <[email protected]> Date: Thu Jan 15 05:22:46 2026 -0800 aarch64: Adjust predicate used for SVE2 SHA3 XAR rotate amount While fixing the Advanced SIMD XAR patterns I looked at SVE2 and it looks okay there but the rotate amount should use the aarch64_simd_rshift_imm predicate rather than lshift_imm since the instruction (unlike the Advanced SIMD version) takes values from [1, bitwidth]. Bootstrapped and tested on aarch64-none-linux-gnu. Signed-off-by: Kyrylo Tkachov <[email protected]> gcc/ PR target/123584 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_xar<mode>): Use aarch64_simd_rshift_imm predicate for rotate amount. Diff: --- gcc/config/aarch64/aarch64-sve2.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index f959837eca0a..c63796542acb 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -1643,7 +1643,7 @@ (xor:SVE_ASIMD_FULL_I (match_operand:SVE_ASIMD_FULL_I 1 "register_operand" "%0,w") (match_operand:SVE_ASIMD_FULL_I 2 "register_operand" "w,w")) - (match_operand:SVE_ASIMD_FULL_I 3 "aarch64_simd_lshift_imm")))] + (match_operand:SVE_ASIMD_FULL_I 3 "aarch64_simd_rshift_imm")))] "TARGET_SVE2 && !(<MODE>mode == V2DImode && TARGET_SHA3)" { operands[3]
