https://gcc.gnu.org/g:3cb7c85eebd985509eae977a45d081b9038ce6ec
commit r16-7064-g3cb7c85eebd985509eae977a45d081b9038ce6ec Author: Wilco Dijkstra <[email protected]> Date: Fri Jan 23 17:48:00 2026 +0000 AArch64: Allow invert for shift counts [PR 123792] Optimize 1 << (31 - x) into 1 << ~x. This fixes part of PR 123792. gcc: PR target/123792 * config/aarch64/aarch64.md (aarch64_<optab>_reg_minus<mode>3): Add support for invert in shift count. gcc/testsuite: PR target/123792 * gcc.target/aarch64/pr123792.c: New test. Diff: --- gcc/config/aarch64/aarch64.md | 8 +++-- gcc/testsuite/gcc.target/aarch64/pr123792.c | 53 +++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 2 deletions(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 568e5814afc2..70a64a6c0ed8 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -6178,7 +6178,8 @@ (match_operand:GPI 1 "register_operand" "r") (minus:QI (match_operand 2 "const_int_operand" "n") (match_operand:QI 3 "register_operand" "r"))))] - "INTVAL (operands[2]) == GET_MODE_BITSIZE (<MODE>mode)" + "INTVAL (operands[2]) == GET_MODE_BITSIZE (<MODE>mode) + || INTVAL (operands[2]) == GET_MODE_BITSIZE (<MODE>mode) - 1" "#" "&& true" [(const_int 0)] @@ -6188,7 +6189,10 @@ rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode) : gen_lowpart (SImode, operands[0])); - emit_insn (gen_negsi2 (tmp, subreg_tmp)); + if (INTVAL (operands[2]) == GET_MODE_BITSIZE (<MODE>mode)) + emit_insn (gen_negsi2 (tmp, subreg_tmp)); + else + emit_insn (gen_one_cmplsi2 (tmp, subreg_tmp)); rtx and_op = gen_rtx_AND (SImode, tmp, GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1)); diff --git a/gcc/testsuite/gcc.target/aarch64/pr123792.c b/gcc/testsuite/gcc.target/aarch64/pr123792.c new file mode 100644 index 000000000000..9e09aa31024f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr123792.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include <stdint.h> + +/* +** f1: +** mvn w1, w1 +** lsl w0, w0, w1 +** ret +*/ + +int f1 (int x, int n) +{ + return x << (31 - n); +} + +/* +** f2: +** mvn w1, w1 +** asr w0, w0, w1 +** ret +*/ + +int f2 (int x, int n) +{ + return x >> (31 - n); +} + +/* +** f3: +** mvn w1, w1 +** lsr x0, x0, x1 +** ret +*/ + +unsigned long f3 (unsigned long long x, int n) +{ + return x >> (63 - n); +} + +/* +** f4: +** mvn w1, w1 +** lsl x0, x0, x1 +** ret +*/ + +long f4 (long x, int n) +{ + return x << (63 - n); +}
