https://gcc.gnu.org/g:06221fe413302f16bbbc22324f98173f45ea9088

commit r16-7558-g06221fe413302f16bbbc22324f98173f45ea9088
Author: Richard Earnshaw <[email protected]>
Date:   Tue Feb 17 16:19:32 2026 +0000

    arm: don't allow movMcc when short-it but no vsel [PR124134]
    
    Perverse combinations of options can lead to the compiler having to
    work around unexpected situations.  Armv8 originally specified that
    complex IT sequences were deprecated for performance (it was later
    rescinded).  If the options restrict the floating-point unit to
    one without vsel, then movMcc patterns need complex IT sequences
    and we can end up with unmatched RTL patterns.  Avoid this by
    failing early when the target patterns are disabled.
    
    gcc/ChangeLog:
    
            PR target/124134
            * config/arm/arm.md (movsfcc): FAIL if using restricted IT
            blocks and we lack VSEL.
            (movdfcc): Likewise.
    
    gcc/testsuite/ChangeLog:
    
            PR target/124134
            * gcc.target/arm/pr124134.c: New test.

Diff:
---
 gcc/config/arm/arm.md                   | 12 ++++++++++--
 gcc/testsuite/gcc.target/arm/pr124134.c | 10 ++++++++++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 4c3f1a5e2af8..a3e6a362fdef 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -8374,9 +8374,13 @@
     enum rtx_code code = GET_CODE (operands[1]);
     rtx ccreg;
 
+    /* Perverse combinations of architecture options can't be supported
+       as they need conditional instructions.  */
+    if (TARGET_THUMB2 && arm_restrict_it && !TARGET_VFP5)
+      FAIL;
     if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0),
                                          &XEXP (operands[1], 1)))
-       FAIL;
+      FAIL;
 
     code = GET_CODE (operands[1]);
     ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
@@ -8396,9 +8400,13 @@
     enum rtx_code code = GET_CODE (operands[1]);
     rtx ccreg;
 
+    /* Perverse combinations of architecture options can't be supported
+       as they need conditional instructions.  */
+    if (TARGET_THUMB2 && arm_restrict_it && !TARGET_VFP5)
+      FAIL;
     if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0), 
                                          &XEXP (operands[1], 1)))
-       FAIL;
+      FAIL;
     code = GET_CODE (operands[1]);
     ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
                                 XEXP (operands[1], 1), NULL_RTX);
diff --git a/gcc/testsuite/gcc.target/arm/pr124134.c 
b/gcc/testsuite/gcc.target/arm/pr124134.c
new file mode 100644
index 000000000000..9d80f95aff9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr124134.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v7a_fp_hard_ok } */
+/* { dg-add-options arm_arch_v7a_fp_hard } */
+/* { dg-additional-options "-O2 -mrestrict-it" } */
+double max___a, max___b;
+double max() {
+  if (max___a < max___b)
+    return max___b;
+  return max___a;
+}

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