https://gcc.gnu.org/g:1ad01d1aa22686fc28c406c5d6678848ed744937
commit r16-7953-g1ad01d1aa22686fc28c406c5d6678848ed744937 Author: Takayuki 'January June' Suwa <[email protected]> Date: Sun Mar 8 17:40:16 2026 +0900 xtensa: Make use of compact insn definition syntax more The remaining MD templates with multiple alternatives will also be re- written using compact syntax. gcc/ChangeLog: * config/xtensa/xtensa.md (movdi_internal, movdf_internal, *btrue, *ubtrue, movsicc_internal0, movsicc_internal1, movsfcc_internal0, movsfcc_internal1): Rewrite in compact syntax. Diff: --- gcc/config/xtensa/xtensa.md | 151 +++++++++++++++++++++++--------------------- 1 file changed, 79 insertions(+), 72 deletions(-) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 639a5788cb3c..a9947c612c27 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -1220,11 +1220,18 @@ }) (define_insn_and_split "movdi_internal" - [(set (match_operand:DI 0 "nonimmed_operand" "=a,a,W,a,a,U") - (match_operand:DI 1 "move_operand" "r,Y,i,T,U,r"))] + [(set (match_operand:DI 0 "nonimmed_operand") + (match_operand:DI 1 "move_operand"))] "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)" - "#" + {@ [cons: =0, 1; attrs: type, length] + [a, r; move, 6] # + [a, Y; load, 6] ^ + [W, i; move, 12] ^ + [a, T; load, 6] ^ + [a, U; load, 6] ^ + [U, r; store, 6] ^ + } "&& reload_completed" [(set (match_dup 0) (match_dup 2)) (set (match_dup 1) (match_dup 3))] @@ -1236,9 +1243,7 @@ std::swap (operands[2], operands[3]); } } - [(set_attr "type" "move,load,move,load,load,store") - (set_attr "mode" "DI") - (set_attr "length" "6,6,12,6,6,6")]) + [(set_attr "mode" "DI")]) ;; 32-bit Integer moves @@ -1503,11 +1508,18 @@ }) (define_insn_and_split "movdf_internal" - [(set (match_operand:DF 0 "nonimmed_operand" "=a,a,W,a,a,U") - (match_operand:DF 1 "move_operand" "r,Y,iF,T,U,r"))] + [(set (match_operand:DF 0 "nonimmed_operand") + (match_operand:DF 1 "move_operand"))] "register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)" - "#" + {@ [cons: =0, 1; attrs: type, length] + [a, r; move, 6] # + [a, Y; load, 6] ^ + [W, iF; move, 12] ^ + [a, T; load, 6] ^ + [a, U; load, 6] ^ + [U, r; store, 6] ^ + } "&& reload_completed" [(set (match_dup 0) (match_dup 2)) (set (match_dup 1) (match_dup 3))] @@ -1519,9 +1531,7 @@ std::swap (operands[2], operands[3]); } } - [(set_attr "type" "move,load,move,load,load,store") - (set_attr "mode" "DF") - (set_attr "length" "6,6,12,6,6,6")]) + [(set_attr "mode" "DF")]) ;; Block moves @@ -1859,16 +1869,16 @@ (define_insn "*btrue" [(set (pc) (if_then_else (match_operator 3 "branch_operator" - [(match_operand:SI 0 "register_operand" "r,r") - (match_operand:SI 1 "branch_operand" "K,?r")]) - (label_ref (match_operand 2 "" "")) + [(match_operand:SI 0 "register_operand") + (match_operand:SI 1 "branch_operand")]) + (label_ref (match_operand 2 "")) (pc)))] "" -{ - return xtensa_emit_branch (which_alternative == 0, operands); -} - [(set_attr "type" "jump,jump") - (set_attr "mode" "none") + {@ [cons: 0, 1, 2; attrs: type] + [r, K, ; jump] << xtensa_emit_branch (true, operands); + [r, ?r, ; jump] << xtensa_emit_branch (false, operands); + } + [(set_attr "mode" "none") (set (attr "length") (if_then_else (match_test "TARGET_DENSITY && CONST_INT_P (operands[1]) @@ -1909,17 +1919,16 @@ (define_insn "*ubtrue" [(set (pc) (if_then_else (match_operator 3 "ubranch_operator" - [(match_operand:SI 0 "register_operand" "r,r") - (match_operand:SI 1 "ubranch_operand" "L,r")]) - (label_ref (match_operand 2 "" "")) + [(match_operand:SI 0 "register_operand") + (match_operand:SI 1 "ubranch_operand")]) + (label_ref (match_operand 2 "")) (pc)))] "" -{ - return xtensa_emit_branch (which_alternative == 0, operands); -} - [(set_attr "type" "jump,jump") - (set_attr "mode" "none") - (set_attr "length" "3,3")]) + {@ [cons: 0, 1, 2; attrs: type, length] + [r, L, ; jump, 3] << xtensa_emit_branch (true, operands); + [r, r, ; jump, 3] << xtensa_emit_branch (false, operands); + } + [(set_attr "mode" "none")]) ;; Branch patterns for bit testing @@ -2373,66 +2382,64 @@ }) (define_insn "movsicc_internal0" - [(set (match_operand:SI 0 "register_operand" "=a,a") + [(set (match_operand:SI 0 "register_operand") (if_then_else:SI (match_operator 4 "branch_operator" - [(match_operand:SI 1 "register_operand" "r,r") + [(match_operand:SI 1 "register_operand") (const_int 0)]) - (match_operand:SI 2 "register_operand" "r,0") - (match_operand:SI 3 "register_operand" "0,r")))] + (match_operand:SI 2 "register_operand") + (match_operand:SI 3 "register_operand")))] "" -{ - return xtensa_emit_movcc (which_alternative == 1, false, false, operands); -} - [(set_attr "type" "move,move") - (set_attr "mode" "SI") - (set_attr "length" "3,3")]) + {@ [cons: =0, 1, 2, 3; attrs: type, length] + [a, r, r, 0; move, 3] << xtensa_emit_movcc (false, false, false, operands); + [a, r, 0, r; move, 3] << xtensa_emit_movcc (true, false, false, operands); + } + [(set_attr "mode" "SI")]) (define_insn "movsicc_internal1" - [(set (match_operand:SI 0 "register_operand" "=a,a") + [(set (match_operand:SI 0 "register_operand") (if_then_else:SI (match_operator 4 "boolean_operator" - [(match_operand:CC 1 "register_operand" "b,b") + [(match_operand:CC 1 "register_operand") (const_int 0)]) - (match_operand:SI 2 "register_operand" "r,0") - (match_operand:SI 3 "register_operand" "0,r")))] + (match_operand:SI 2 "register_operand") + (match_operand:SI 3 "register_operand")))] "TARGET_BOOLEANS" -{ - return xtensa_emit_movcc (which_alternative == 1, false, true, operands); -} - [(set_attr "type" "move,move") - (set_attr "mode" "SI") - (set_attr "length" "3,3")]) + {@ [cons: =0, 1, 2, 3; attrs: type, length] + [a, b, r, 0; move, 3] << xtensa_emit_movcc (false, false, true, operands); + [a, b, 0, r; move, 3] << xtensa_emit_movcc (true, false, true, operands); + } + [(set_attr "mode" "SI")]) (define_insn "movsfcc_internal0" - [(set (match_operand:SF 0 "register_operand" "=a,a,f,f") + [(set (match_operand:SF 0 "register_operand") (if_then_else:SF (match_operator 4 "branch_operator" - [(match_operand:SI 1 "register_operand" "r,r,r,r") + [(match_operand:SI 1 "register_operand") (const_int 0)]) - (match_operand:SF 2 "register_operand" "r,0,f,0") - (match_operand:SF 3 "register_operand" "0,r,0,f")))] - "" -{ - return xtensa_emit_movcc ((which_alternative & 1) == 1, - which_alternative >= 2, false, operands); -} - [(set_attr "type" "move,move,move,move") - (set_attr "mode" "SF") - (set_attr "length" "3,3,3,3")]) + (match_operand:SF 2 "register_operand") + (match_operand:SF 3 "register_operand")))] + "" + {@ [cons: =0, 1, 2, 3; attrs: type, length] + [a, r, r, 0; move, 3] << xtensa_emit_movcc (false, false, false, operands); + [a, r, 0, r; move, 3] << xtensa_emit_movcc (true, false, false, operands); + [f, r, f, 0; move, 3] << xtensa_emit_movcc (false, true, false, operands); + [f, r, 0, f; move, 3] << xtensa_emit_movcc (true, true, false, operands); + } + [(set_attr "mode" "SF")]) (define_insn "movsfcc_internal1" - [(set (match_operand:SF 0 "register_operand" "=a,a,f,f") + [(set (match_operand:SF 0 "register_operand") (if_then_else:SF (match_operator 4 "boolean_operator" - [(match_operand:CC 1 "register_operand" "b,b,b,b") + [(match_operand:CC 1 "register_operand") (const_int 0)]) - (match_operand:SF 2 "register_operand" "r,0,f,0") - (match_operand:SF 3 "register_operand" "0,r,0,f")))] + (match_operand:SF 2 "register_operand") + (match_operand:SF 3 "register_operand")))] "TARGET_BOOLEANS" -{ - return xtensa_emit_movcc ((which_alternative & 1) == 1, - which_alternative >= 2, true, operands); -} - [(set_attr "type" "move,move,move,move") - (set_attr "mode" "SF") - (set_attr "length" "3,3,3,3")]) + {@ [cons: =0, 1, 2, 3; attrs: type, length] + [a, b, r, 0; move, 3] << xtensa_emit_movcc (false, false, true, operands); + [a, b, 0, r; move, 3] << xtensa_emit_movcc (true, false, true, operands); + [f, b, f, 0; move, 3] << xtensa_emit_movcc (false, true, true, operands); + [f, b, 0, f; move, 3] << xtensa_emit_movcc (true, true, true, operands); + } + [(set_attr "mode" "SF")]) ;; Floating-point comparisons.
