https://gcc.gnu.org/g:82f9c2a2abea7fd020deeb5887c44af52b7bca88

commit 82f9c2a2abea7fd020deeb5887c44af52b7bca88
Author: Alexandre Oliva <[email protected]>
Date:   Tue Mar 10 04:20:45 2026 -0300

    testsuite: vect: ppc: vect-100 fails invalid sum [PR119293]
    
    A few more tests hit 'Invalid sum' failures on powerpc-elf.
    
    Though the failures occur at different spots in the optimization
    pipeline, they're all variants of the same pattern described in the
    PR: we resolve a condition introduced by the vectorizer to a constant,
    drop an edge from the CFG, adjust the probability of the remaining
    edge, but fail to adjust subsequent execution counts accordingly.
    
    Document the observations as comments in the tests, and mark them as
    expected failures.
    
    
    for  gcc/testsuite/ChangeLog
    
            PR tree-optimization/119293
            * gcc.dg/vect/vect-100.c: Expect Invalid sum failure on
            powerpc variants without means to handle unaligned stores.
            * gcc.dg/vect/vect-121.c: Likewise.
            * gcc.dg/vect/vect-epilogues.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.dg/vect/vect-100.c       | 5 ++++-
 gcc/testsuite/gcc.dg/vect/vect-121.c       | 7 ++++++-
 gcc/testsuite/gcc.dg/vect/vect-epilogues.c | 6 +++++-
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/vect-100.c 
b/gcc/testsuite/gcc.dg/vect/vect-100.c
index dd4c2c0bec88..e42ff4183d25 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-100.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-100.c
@@ -80,4 +80,7 @@ int main (void)
 /* Requires versioning.  */
 /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 0 "vect" } } */
 
-/* { dg-final { scan-tree-dump-not "Invalid sum" "optimized" } } */
+/* When we don't have misaligned stores, the vectorized loop is conditional,
+   and the condition and the vectorized loop are optimized out in ccp4, leaving
+   the estimated counts of the fallback non-vector loop incorrect.  */
+/* { dg-final { scan-tree-dump-not "Invalid sum" "optimized" { xfail { 
powerpc*-*-* && { vect_no_store_align && { ! vect_hw_misalign } } } } } } */ /* 
PR 119293 */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-121.c 
b/gcc/testsuite/gcc.dg/vect/vect-121.c
index 1b9357d82a28..66305f5afc2c 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-121.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-121.c
@@ -16,4 +16,9 @@ test (int start, int end)
 }
 
 /* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" } } */
-/* { dg-final { scan-tree-dump-not "Invalid sum" "optimized" { xfail ia32 } } 
} */
+/* If we need a non-vectorized prologue to align the stores for a vectorized
+   loop, the vectorizer may introduce a condition that eventually resolves to a
+   constant, and the removal of the edge and recomputation of probabilities
+   gets estimated execution counts wrong.  On ia32, the condition is resolved
+   in fre5; on powerpc-elf, in dom3.  */
+/* { dg-final { scan-tree-dump-not "Invalid sum" "optimized" { xfail { ia32 || 
{ powerpc*-*-* && { vect_no_store_align && { ! vect_hw_misalign } } } } } } } 
*/ /* PR 119293 */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-epilogues.c 
b/gcc/testsuite/gcc.dg/vect/vect-epilogues.c
index a444071b816e..207b177954ba 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-epilogues.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-epilogues.c
@@ -18,4 +18,8 @@ void pixel_avg( unsigned char *dst, int i_dst_stride,
  }
 
 /* { dg-final { scan-tree-dump "LOOP EPILOGUE VECTORIZED" "vect" { target 
vect_multiple_sizes xfail { { arm32 && be } || vect_partial_vectors_usage_2 } } 
} } */
-/* { dg-final { scan-tree-dump-not "Invalid sum" "optimized" { xfail 
sparc-leon3-elf s390x-*-* powerpc64le-*-* } } } */
+/* The condition that selects between the vectorized loop (with prologue and
+   epilogue for alignment) and a non-vectorized version may resolve to a
+   constant, and the removal of the edge doesn't adjust estimated execution
+   counts.  */
+/* { dg-final { scan-tree-dump-not "Invalid sum" "optimized" { xfail { { 
sparc-leon3-elf s390x-*-* powerpc64le-*-* } || { powerpc*-*-* && { 
vect_no_store_align && { ! vect_hw_misalign } } } } } } } */ /* PR 119293 */

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