https://gcc.gnu.org/g:7f3cd93e4c324858e88c382fdc85dade9b6fdfb3
commit 7f3cd93e4c324858e88c382fdc85dade9b6fdfb3 Author: Michael Meissner <[email protected]> Date: Wed Mar 11 17:59:45 2026 -0400 Revert changes Diff: --- gcc/ChangeLog.dmf | 127 --------------------- gcc/config/rs6000/constraints.md | 10 -- gcc/config/rs6000/predicates.md | 52 +-------- gcc/config/rs6000/rs6000-string.cc | 1 - gcc/config/rs6000/rs6000.cc | 25 ---- gcc/config/rs6000/rs6000.h | 7 -- gcc/config/rs6000/rs6000.md | 110 +++--------------- gcc/config/rs6000/vsx.md | 122 ++++---------------- gcc/testsuite/gcc.target/powerpc/lxvrl.c | 32 ------ gcc/testsuite/gcc.target/powerpc/prefixed-addis.c | 24 ---- .../gcc.target/powerpc/saturate-subtract-1.c | 38 ------ .../gcc.target/powerpc/saturate-subtract-2.c | 38 ------ 12 files changed, 35 insertions(+), 551 deletions(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf index 2868e7a43e32..ee7f1564c684 100644 --- a/gcc/ChangeLog.dmf +++ b/gcc/ChangeLog.dmf @@ -1,130 +1,3 @@ -==================== Branch work238-dmf, patch #112 ==================== - -Add paddis support. - -This patch adds support for the paddis instruction that might be added to a -future PowerPC processor. - -gcc/ - -2026-03-11 Michael Meissner <[email protected]> - - * config/rs6000/constraints.md (eU): New constraint. - (eV): Likewise. - * config/rs6000/predicates.md (paddis_operand): New predicate. - (paddis_paddi_operand): Likewise. - (add_operand): Add paddis support. - * config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis support. - (num_insns_constant_multi): Likewise. - (print_operand): Add %B<n> for paddis support. - * config/rs6000/rs6000.h (TARGET_PADDIS): New macro. - (SIGNED_INTEGER_32BIT_P): Likewise. - * config/rs6000/rs6000.md (isa attribute): Add paddis support. - (enabled attribute); Likewise. - (add<mode>3): Likewise. - (adddi3 splitter): New splitter for paddis. - (movdi_internal64): Add paddis support. - (movdi splitter): New splitter for paddis. - -gcc/testsuite/ - -2026-03-11 Michael Meissner <[email protected]> - - * gcc.target/powerpc/prefixed-addis.c: New test. - -==================== Branch work238-dmf, patch #112 ==================== - -Support load/store vector with right length. - -This patch adds support for new instructions that may be added to the PowerPC -architecture in the future to enhance the load and store vector with length -instructions. - -The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use -since the count for the number of bytes must be in the top 8 bits of the GPR -register, instead of the bottom 8 bits. This meant that code generating these -instructions typically had to do a shift left by 56 bits to get the count into -the right position. In a future version of the PowerPC architecture, new -variants of these instructions might be added that expect the count to be in -the bottom 8 bits of the GPR register. These patches add this support to GCC -if the user uses the -mcpu=future option. - -I discovered that the code in rs6000-string.cc to generate ISA 3.1 lxvl/stxvl -future lxvll/stxvll instructions would generate these instructions on 32-bit. -However the patterns for these instructions is only done on 64-bit systems. So -I added a check for 64-bit support before generating the instructions. - -The patches have been tested on both little and big endian systems. Can I check -it into the master branch? - -gcc/ - -2026-03-11 Michael Meissner <[email protected]> - - * config/rs6000/rs6000-string.cc (expand_block_move): Do not generate - lxvl and stxvl on 32-bit. - * config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl with - the shift count automaticaly used in the insn. - (lxvrl): New insn for -mcpu=future. - (lxvrll): Likewise. - (stxvl): If -mcpu=future, generate the stxvl with the shift count - automaticaly used in the insn. - (stxvrl): New insn for -mcpu=future. - (stxvrll): Likewise. - -gcc/testsuite/ - -2026-03-11 Michael Meissner <[email protected]> - - * gcc.target/powerpc/lxvrl.c: New test. - -==================== Branch work238-dmf, patch #111 ==================== - -Add xvrlw support. - -This patch adds support for a possible new variant of the vector rotate left -instruction that might be added to a future PowerPC. This variant (xvrlw) can -use any VSX register instead of requiring only Altivec registers. - -gcc/ - -2026-03-11 Michael Meissner <[email protected]> - - * config/rs6000/altivec.md (xvrlw): New insn. - * config/rs6000/rs6000.h (TARGET_XVRLW): New macro. - -2026-03-11 Michael Meissner <[email protected]> - -gcc/testsuite/ - - * gcc.target/powerpc/vector-rotate-left.c: New test. - -==================== Branch work238-dmf, patch #110 ==================== - -Add saturate subtract support - -This patch adds support for saturating subtract instructions that might be added -to a future PowerPC. I think I had originally submitted patches that added a -new built-in function to generate the subfus and subdus instructions. Segher -suggested that instead of generating a built-in function, that I should just -having GCC automatically recognize cases where a saturating subtract could be -generated. This patch generates the saturating subtract instructions in the -appropriate context. - -gcc/ - -2026-03-11 Michael Meissner <[email protected]> - - * config/rs6000/rs6000.md (gtu_geu): New code iterator. - (subfus<mode>3_<code>): New insns. - -gcc/testsuite/ - -2026-03-11 Michael Meissner <[email protected]> - - * gcc.target/powerpc/saturate-subtract-1.c: New test. - * gcc.target/powerpc/saturate-subtract-2.c: Likewise. - ==================== Branch work238-dmf, patch #104 ==================== Add support for 1,024 bit dense math registers. diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index a755fb31df81..0d1cde5bd4de 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -222,16 +222,6 @@ "An IEEE 128-bit constant that can be loaded into VSX registers." (match_operand 0 "easy_vector_constant_ieee128")) -(define_constraint "eU" - "@internal integer constant that can be loaded with paddis" - (and (match_code "const_int") - (match_operand 0 "paddis_operand"))) - -(define_constraint "eV" - "@internal integer constant that can be loaded with paddis + paddi" - (and (match_code "const_int") - (match_operand 0 "paddis_paddi_operand"))) - ;; Floating-point constraints. These two are defined so that insn ;; length attributes can be calculated exactly. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 6a6eb4f36539..8221e0fa2d05 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -378,53 +378,6 @@ return SIGNED_INTEGER_34BIT_P (INTVAL (op)); }) -;; Return 1 if op is a 64-bit constant that uses the paddis instruction -(define_predicate "paddis_operand" - (match_code "const_int") -{ - if (!TARGET_PADDIS && TARGET_POWERPC64) - return 0; - - /* If addi, addis, or paddi can handle the number, don't return true. */ - HOST_WIDE_INT value = INTVAL (op); - if (SIGNED_INTEGER_34BIT_P (value)) - return false; - - /* If the number is too large for padds, return false. */ - if (!SIGNED_INTEGER_32BIT_P (value >> 32)) - return false; - - /* If the bottom 32-bits are non-zero, paddis can't handle it. */ - if ((value & HOST_WIDE_INT_C(0xffffffff)) != 0) - return false; - - return true; -}) - -;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an -;; addi/addis/paddi instruction combination. -(define_predicate "paddis_paddi_operand" - (match_code "const_int") -{ - if (!TARGET_PADDIS && TARGET_POWERPC64) - return 0; - - /* If addi, addis, or paddi can handle the number, don't return true. */ - HOST_WIDE_INT value = INTVAL (op); - if (SIGNED_INTEGER_34BIT_P (value)) - return false; - - /* If the number is too large for padds, return false. */ - if (!SIGNED_INTEGER_32BIT_P (value >> 32)) - return false; - - /* If the bottom 32-bits are zero, we can use paddis alone to handle it. */ - if ((value & HOST_WIDE_INT_C(0xffffffff)) == 0) - return false; - - return true; -}) - ;; Return 1 if op is a register that is not special. ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where ;; you need to be careful in moving a SFmode to SImode and vice versa due to @@ -1169,10 +1122,7 @@ (if_then_else (match_code "const_int") (match_test "satisfies_constraint_I (op) || satisfies_constraint_L (op) - || satisfies_constraint_eI (op) - || satisfies_constraint_eU (op) - || satisfies_constraint_eV (op)") - + || satisfies_constraint_eI (op)") (match_operand 0 "gpc_reg_operand"))) ;; Return 1 if the operand is either a non-special register, or 0, or -1. diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index faa6ee049f0c..35bb259c0242 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -2786,7 +2786,6 @@ expand_block_move (rtx operands[], bool might_overlap) if (TARGET_MMA && TARGET_BLOCK_OPS_UNALIGNED_VSX && TARGET_BLOCK_OPS_VECTOR_PAIR - && TARGET_POWERPC64 && bytes >= 32 && (align >= 256 || !STRICT_ALIGNMENT)) { diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 61c12a06f10e..6ff58f577f1c 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4327,7 +4327,6 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_PCREL; } - /* Print the options after updating the defaults. */ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags); @@ -6168,14 +6167,6 @@ num_insns_constant_gpr (HOST_WIDE_INT value) else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value)) return 1; - /* PADDIS support. */ - else if (TARGET_PADDIS && TARGET_POWERPC64 - && !IN_RANGE (value >> 32, -1, 0) - && (SIGNED_INTEGER_32BIT_P (value >> 32))) - return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0 - ? 1 - : 2); - else if (TARGET_POWERPC64) { int num_insns = 0; @@ -6196,14 +6187,6 @@ num_insns_constant_multi (HOST_WIDE_INT value, machine_mode mode) { int nregs = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; int total = 0; - if (nregs == 1 - && TARGET_PADDIS && TARGET_POWERPC64 - && !IN_RANGE (value >> 32, -1, 0) - && SIGNED_INTEGER_32BIT_P (value >> 32)) - return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0 - ? 1 - : 2); - while (nregs-- > 0) { HOST_WIDE_INT low = sext_hwi (value, BITS_PER_WORD); @@ -14294,14 +14277,6 @@ print_operand (FILE *file, rtx x, int code) fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4); return; - case 'B': - /* Upper 32-bits of a constant. */ - if (!CONST_INT_P (x)) - output_operand_lossage ("Not a constant."); - - fprintf (file, "%" HOST_LONG_FORMAT "d", INTVAL (x) >> 32); - return; - case 'D': /* Like 'J' but get to the GT bit only. */ if (!REG_P (x) || !CR_REGNO_P (REGNO (x))) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 88a8717a9d85..23cef83ba17e 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -567,12 +567,6 @@ extern int rs6000_vector_align[]; below. */ #define RS6000_FN_TARGET_INFO_HTM 1 -/* Whether we have XVRLW support. */ -#define TARGET_XVRLW TARGET_FUTURE - -/* Whether we have PADDIS support. */ -#define TARGET_PADDIS TARGET_FUTURE - /* Whether the various reciprocal divide/square root estimate instructions exist, and whether we should automatically generate code for the instruction by default. */ @@ -2490,7 +2484,6 @@ typedef struct GTY(()) machine_function (HOST_WIDE_INT_1 << ((N)-1)) - 1) #define SIGNED_INTEGER_16BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 16) -#define SIGNED_INTEGER_32BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 32) #define SIGNED_INTEGER_34BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 34) /* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 7fc34f2bb34b..57a239791ee3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -371,7 +371,7 @@ (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,paddis" +(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10" (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? @@ -423,11 +423,6 @@ (and (eq_attr "isa" "p10") (match_test "TARGET_POWER10")) (const_int 1) - - (and (eq_attr "isa" "paddis") - (match_test "TARGET_PADDIS")) - (const_int 1) - ] (const_int 0))) ;; If this instruction is microcoded on the CELL processor @@ -1850,42 +1845,17 @@ }) (define_insn "*add<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r,r,b") - (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b,b,b") - (match_operand:GPR 2 "add_operand" "r,I,L,eI,eU,eV")))] + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b") + (match_operand:GPR 2 "add_operand" "r,I,L,eI")))] "" "@ add %0,%1,%2 addi %0,%1,%2 addis %0,%1,%v2 - addi %0,%1,%2 - paddis %0,%1,%B2 - #" + addi %0,%1,%2" [(set_attr "type" "add") - (set_attr "isa" "*,*,*,p10,paddis,paddis") - (set_attr "length" "*,*,*,*,12,24") - (set_attr "prefixed" "*,*,*,*,yes,yes") - (set_attr "maybe_prefixed" "*,*,*,*,no,no")]) - -(define_split - [(set (match_operand:DI 0 "gpc_reg_operand") - (plus:DI (match_operand:DI 1 "gpc_reg_operand") - (match_operand:DI 2 "paddis_paddi_operand")))] - "TARGET_PADDIS && TARGET_POWERPC64" - [(set (match_dup 3) - (plus:DI (match_dup 1) - (match_dup 4))) - (set (match_dup 0) - (plus:DI (match_dup 3) - (match_dup 5)))] -{ - HOST_WIDE_INT value = INTVAL (operands[2]); - operands[3] = (can_create_pseudo_p () - ? gen_reg_rtx (DImode) - : operands[0]); - operands[4] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff)); - operands[5] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff)); -}) + (set_attr "isa" "*,*,*,p10")]) (define_insn "*addsi3_high" [(set (match_operand:SI 0 "gpc_reg_operand" "=b") @@ -2427,20 +2397,6 @@ "" ) -;; Saturating subtract -(define_code_iterator gtu_geu [gtu geu]) - -(define_insn "*subfus<mode>3_<code>" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (if_then_else:GPR (gtu_geu (match_operand:GPR 2 "gpc_reg_operand" "r") - (match_operand:GPR 1 "gpc_reg_operand" "r")) - (minus:GPR (match_dup 2) - (match_dup 1)) - (const_int 0)))] - "TARGET_FUTURE" - "sub<wd>us %0,%1,%2" - [(set_attr "type" "add")]) - (define_insn "@neg<mode>2" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] @@ -9908,7 +9864,7 @@ DONE; }) -;; GPR store GPR load GPR move GPR paddis GPR paddis+paddi +;; GPR store GPR load GPR move ;; GPR li GPR lis GPR pli GPR # ;; FPR store FPR load FPR move ;; AVX store AVX store AVX load AVX load VSX move @@ -9918,7 +9874,7 @@ ;; VSX->GPR GPR->VSX (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" - "=YZ, r, r, r, b, + "=YZ, r, r, r, r, r, r, m, ^d, ^d, wY, Z, $v, $v, ^wa, @@ -9927,7 +9883,7 @@ r, *h, *h, ?r, ?wa") (match_operand:DI 1 "input_operand" - "r, YZ, r, eU, eV, + "r, YZ, r, I, L, eI, nF, ^d, m, ^d, ^v, $v, wY, Z, ^wa, @@ -9942,8 +9898,6 @@ std%U0%X0 %1,%0 ld%U1%X1 %0,%1 mr %0,%1 - paddis %0,0,%B1 - # li %0,%1 lis %0,%v1 li %0,%1 @@ -9969,7 +9923,7 @@ mfvsrd %0,%x1 mtvsrd %x0,%1" [(set_attr "type" - "store, load, *, *, *, + "store, load, *, *, *, *, *, fpstore, fpload, fpsimple, fpstore, fpstore, fpload, fpload, veclogical, @@ -9979,7 +9933,7 @@ mfvsr, mtvsr") (set_attr "size" "64") (set_attr "length" - "*, *, *, 12, 24, + "*, *, *, *, *, *, 20, *, *, *, *, *, *, *, *, @@ -9988,32 +9942,14 @@ *, *, *, *, *") (set_attr "isa" - "*, *, *, paddis, paddis, + "*, *, *, *, *, p10, *, *, *, *, p9v, p7v, p9v, p7v, *, p9v, p9v, p7v, *, *, p7v, p7v, *, *, *, - p8v, p8v") - (set_attr "prefixed" - "*, *, *, yes, yes, - *, *, *, *, - *, *, *, - *, *, *, *, *, - *, *, *, *, *, - *, *, - *, *, *, - *, *") - (set_attr "maybe_prefixed" - "*, *, *, no, no, - *, *, *, *, - *, *, *, - *, *, *, *, *, - *, *, *, *, *, - *, *, - *, *, *, - *, *")]) + p8v, p8v")]) ; Some DImode loads are best done as a load of -1 followed by a mask ; instruction. @@ -10031,26 +9967,6 @@ (match_dup 1)))] "") -;; Split a constant that can be generated by a paddis and paddi into 2 -;; instructions. -(define_split - [(set (match_operand:DI 0 "int_reg_operand") - (match_operand:DI 1 "paddis_paddi_operand"))] - "TARGET_PADDIS && TARGET_POWERPC64" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (plus:DI (match_dup 2) - (match_dup 4)))] -{ - HOST_WIDE_INT value = INTVAL (operands[1]); - operands[2] = (can_create_pseudo_p () - ? gen_reg_rtx (DImode) - : operands[0]); - operands[3] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff)); - operands[4] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff)); -}) - ;; Split a load of a large constant into the appropriate five-instruction ;; sequence. Handle anything in a constant number of insns. ;; When non-easy constants can go in the TOC, this should use diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index c162467571f9..cfad9b8c6d54 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5712,32 +5712,20 @@ DONE; }) -;; Load VSX Vector with Length. If we have lxvrl, we don't have to do an -;; explicit shift left into a pseudo. +;; Load VSX Vector with Length (define_expand "lxvl" - [(use (match_operand:V16QI 0 "vsx_register_operand")) - (use (match_operand:DI 1 "gpc_reg_operand")) - (use (match_operand:DI 2 "gpc_reg_operand"))] + [(set (match_dup 3) + (ashift:DI (match_operand:DI 2 "register_operand") + (const_int 56))) + (set (match_operand:V16QI 0 "vsx_register_operand") + (unspec:V16QI + [(match_operand:DI 1 "gpc_reg_operand") + (mem:V16QI (match_dup 1)) + (match_dup 3)] + UNSPEC_LXVL))] "TARGET_P9_VECTOR && TARGET_64BIT" { - rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56)); - rtx len; - - if (TARGET_FUTURE) - len = shift_len; - else - { - len = gen_reg_rtx (DImode); - emit_insn (gen_rtx_SET (len, shift_len)); - } - - rtx dest = operands[0]; - rtx addr = operands[1]; - rtx mem = gen_rtx_MEM (V16QImode, addr); - rtvec rv = gen_rtvec (3, addr, mem, len); - rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL); - emit_insn (gen_rtx_SET (dest, lxvl)); - DONE; + operands[3] = gen_reg_rtx (DImode); }) (define_insn "*lxvl" @@ -5761,34 +5749,6 @@ "lxvll %x0,%1,%2" [(set_attr "type" "vecload")]) -;; For lxvrl and lxvrll, use the combiner to eliminate the shift. The -;; define_expand for lxvl will already incorporate the shift in generating the -;; insn. The lxvll buitl-in function required the user to have already done -;; the shift. Defining lxvrll this way, will optimize cases where the user has -;; done the shift immediately before the built-in. -(define_insn "*lxvrl" - [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") - (unspec:V16QI - [(match_operand:DI 1 "gpc_reg_operand" "b") - (mem:V16QI (match_dup 1)) - (ashift:DI (match_operand:DI 2 "register_operand" "r") - (const_int 56))] - UNSPEC_LXVL))] - "TARGET_FUTURE && TARGET_64BIT" - "lxvrl %x0,%1,%2" - [(set_attr "type" "vecload")]) - -(define_insn "*lxvrll" - [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") - (unspec:V16QI [(match_operand:DI 1 "gpc_reg_operand" "b") - (mem:V16QI (match_dup 1)) - (ashift:DI (match_operand:DI 2 "register_operand" "r") - (const_int 56))] - UNSPEC_LXVLL))] - "TARGET_FUTURE" - "lxvrll %x0,%1,%2" - [(set_attr "type" "vecload")]) - ;; Expand for builtin xl_len_r (define_expand "xl_len_r" [(match_operand:V16QI 0 "vsx_register_operand") @@ -5820,29 +5780,18 @@ ;; Store VSX Vector with Length (define_expand "stxvl" - [(use (match_operand:V16QI 0 "vsx_register_operand")) - (use (match_operand:DI 1 "gpc_reg_operand")) - (use (match_operand:DI 2 "gpc_reg_operand"))] + [(set (match_dup 3) + (ashift:DI (match_operand:DI 2 "register_operand") + (const_int 56))) + (set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand")) + (unspec:V16QI + [(match_operand:V16QI 0 "vsx_register_operand") + (mem:V16QI (match_dup 1)) + (match_dup 3)] + UNSPEC_STXVL))] "TARGET_P9_VECTOR && TARGET_64BIT" { - rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56)); - rtx len; - - if (TARGET_FUTURE) - len = shift_len; - else - { - len = gen_reg_rtx (DImode); - emit_insn (gen_rtx_SET (len, shift_len)); - } - - rtx src = operands[0]; - rtx addr = operands[1]; - rtx mem = gen_rtx_MEM (V16QImode, addr); - rtvec rv = gen_rtvec (3, src, mem, len); - rtx stxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_STXVL); - emit_insn (gen_rtx_SET (mem, stxvl)); - DONE; + operands[3] = gen_reg_rtx (DImode); }) ;; Define optab for vector access with length vectorization exploitation. @@ -5887,35 +5836,6 @@ "stxvl %x0,%1,%2" [(set_attr "type" "vecstore")]) -;; For stxvrl and stxvrll, use the combiner to eliminate the shift. The -;; define_expand for stxvl will already incorporate the shift in generating the -;; insn. The stxvll buitl-in function required the user to have already done -;; the shift. Defining stxvrll this way, will optimize cases where the user -;; has done the shift immediately before the built-in. - -(define_insn "*stxvrl" - [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b")) - (unspec:V16QI - [(match_operand:V16QI 0 "vsx_register_operand" "wa") - (mem:V16QI (match_dup 1)) - (ashift:DI (match_operand:DI 2 "register_operand" "r") - (const_int 56))] - UNSPEC_STXVL))] - "TARGET_FUTURE && TARGET_64BIT" - "stxvrl %x0,%1,%2" - [(set_attr "type" "vecstore")]) - -(define_insn "*stxvrll" - [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b")) - (unspec:V16QI [(match_operand:V16QI 0 "vsx_register_operand" "wa") - (mem:V16QI (match_dup 1)) - (ashift:DI (match_operand:DI 2 "register_operand" "r") - (const_int 56))] - UNSPEC_STXVLL))] - "TARGET_FUTURE" - "stxvrll %x0,%1,%2" - [(set_attr "type" "vecstore")]) - ;; Expand for builtin xst_len_r (define_expand "xst_len_r" [(match_operand:V16QI 0 "vsx_register_operand" "=wa") diff --git a/gcc/testsuite/gcc.target/powerpc/lxvrl.c b/gcc/testsuite/gcc.target/powerpc/lxvrl.c deleted file mode 100644 index 71854c50c911..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/lxvrl.c +++ /dev/null @@ -1,32 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target powerpc_future_ok } */ -/* { dg-require-effective-target lp64 } */ -/* { dg-options "-mdejagnu-cpu=future -O2" } */ - -/* Test whether the lxvrl and stxvrl instructions are generated for - -mcpu=future on memory copy operations. */ - -#ifndef VSIZE -#define VSIZE 2 -#endif - -#ifndef LSIZE -#define LSIZE 5 -#endif - -struct foo { - vector unsigned char vc[VSIZE]; - unsigned char leftover[LSIZE]; -}; - -void memcpy_ptr (struct foo *p, struct foo *q) -{ - __builtin_memcpy ((void *) p, /* lxvrl and stxvrl. */ - (void *) q, - (sizeof (vector unsigned char) * VSIZE) + LSIZE); -} - -/* { dg-final { scan-assembler {\mlxvrl\M} } } */ -/* { dg-final { scan-assembler {\mstxvrl\M} } } */ -/* { dg-final { scan-assembler-not {\mlxvl\M} } } */ -/* { dg-final { scan-assembler-not {\mstxvl\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/prefixed-addis.c b/gcc/testsuite/gcc.target/powerpc/prefixed-addis.c deleted file mode 100644 index d08e3675f94c..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/prefixed-addis.c +++ /dev/null @@ -1,24 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target powerpc_future_ok } */ -/* { dg-require-effective-target lp64 } */ -/* { dg-options "-mdejagnu-cpu=future -O2" } */ - -/* Test whether the xvrl (vector word rotate left using VSX registers insead of - Altivec registers is generated. */ - -#include <stddef.h> - -size_t -prefix_addis_addi (size_t x) -{ - return x + 0x123456789ABCDEUL; /* paddis + paddi. */ -} - -size_t -prefix_addis (size_t x) -{ - return x + 0x12345600000000UL; /* paddis. */ -} - -/* { dg-final { scan-assembler-times {\mpaddis\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/saturate-subtract-1.c b/gcc/testsuite/gcc.target/powerpc/saturate-subtract-1.c deleted file mode 100644 index 5b3bd2ba0633..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/saturate-subtract-1.c +++ /dev/null @@ -1,38 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-mdejagnu-cpu=future -O2" } */ - -/* Check that saturating subtract (subfus) is generated. Check that all - combinations of >, >=, <, and <= are optimized. */ - -#ifndef TYPE -#define TYPE unsigned int -#endif - -void -saturated_subtract_gt (TYPE a, TYPE b, TYPE *p) -{ - *p = (a > b) ? a - b : 0; -} - -void -saturated_subtract_ge (TYPE a, TYPE b, TYPE *p) -{ - *p = (a >= b) ? a - b : 0; -} - -void -saturated_subtract_lt (TYPE a, TYPE b, TYPE *p) -{ - *p = (a < b) ? 0 : a - b; -} - -void -saturated_subtract_le (TYPE a, TYPE b, TYPE *p) -{ - *p = (a <= b) ? 0 : a - b; -} - -/* { dg-final { scan-assembler-times {\msubfus\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mcmplw\M} } } */ -/* { dg-final { scan-assembler-not {\misel\M} } } */ -/* { dg-final { scan-assembler-not {\msubf\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/saturate-subtract-2.c b/gcc/testsuite/gcc.target/powerpc/saturate-subtract-2.c deleted file mode 100644 index fa8fba2a6339..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/saturate-subtract-2.c +++ /dev/null @@ -1,38 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-mdejagnu-cpu=future -O2" } */ - -/* Check that saturating subtract (subfus) is generated. Check that all - combinations of >, >=, <, and <= are optimized. */ - -#ifndef TYPE -#define TYPE unsigned long -#endif - -void -saturated_subtract_gt (TYPE a, TYPE b, TYPE *p) -{ - *p = (a > b) ? a - b : 0; -} - -void -saturated_subtract_ge (TYPE a, TYPE b, TYPE *p) -{ - *p = (a >= b) ? a - b : 0; -} - -void -saturated_subtract_lt (TYPE a, TYPE b, TYPE *p) -{ - *p = (a < b) ? 0 : a - b; -} - -void -saturated_subtract_le (TYPE a, TYPE b, TYPE *p) -{ - *p = (a <= b) ? 0 : a - b; -} - -/* { dg-final { scan-assembler-times {\msubdus\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mcmpld\M} } } */ -/* { dg-final { scan-assembler-not {\misel\M} } } */ -/* { dg-final { scan-assembler-not {\msubf\M} } } */
