https://gcc.gnu.org/g:09fe5ceba6f1ed7f1ee8fdc79a702ebff3d7d103

commit r16-8892-g09fe5ceba6f1ed7f1ee8fdc79a702ebff3d7d103
Author: Stefan Schulze Frielinghaus <[email protected]>
Date:   Fri May 1 09:16:48 2026 +0200

    s390: Fix dealing with HF vector modes in s390_secondary_reload
    
    Initial HF mode support was added in commit r16-6682-g5d6d56d837c which
    is missing HF vector mode support when dealing with secondary reloads
    for instructions which do not accept relative operands.
    
    gcc/ChangeLog:
    
            * config/s390/s390.cc (s390_secondary_reload): Add cases for HF
            vector modes.
            * config/s390/s390.md: Add modes V{1,2,4,8}HF to mode iterator
            ALL.
    
    (cherry picked from commit c97767d716303fd74aa8a5aa4c3a5c4aea8c9d99)

Diff:
---
 gcc/config/s390/s390.cc | 4 ++++
 gcc/config/s390/s390.md | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index a8afef3222bb..67e002eed3ac 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -5038,6 +5038,10 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t 
rclass_i,
              __SECONDARY_RELOAD_CASE (V1DI, v1di);
              __SECONDARY_RELOAD_CASE (V2DI, v2di);
              __SECONDARY_RELOAD_CASE (V1TI, v1ti);
+             __SECONDARY_RELOAD_CASE (V1HF, v1hf);
+             __SECONDARY_RELOAD_CASE (V2HF, v2hf);
+             __SECONDARY_RELOAD_CASE (V4HF, v4hf);
+             __SECONDARY_RELOAD_CASE (V8HF, v8hf);
              __SECONDARY_RELOAD_CASE (V1SF, v1sf);
              __SECONDARY_RELOAD_CASE (V2SF, v2sf);
              __SECONDARY_RELOAD_CASE (V4SF, v4sf);
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 7219c9b4a6db..0f3222827c7a 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -748,7 +748,8 @@
 
 (define_mode_iterator ALL [TI DI SI HI QI TF FPRX2 DF SF HF TD DD SD V1QI V2QI
                           V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI
-                          V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
+                          V1DI V2DI V1HF V2HF V4HF V8HF V1SF V2SF V4SF
+                          V1TI V1DF V2DF V1TF])
 
 ;; These mode iterators allow floating point patterns to be generated from the
 ;; same template.

Reply via email to