https://gcc.gnu.org/g:bb0cbdac196986de933f4f93097de021c3686d7c
commit r17-446-gbb0cbdac196986de933f4f93097de021c3686d7c Author: Takayuki 'January June' Suwa <[email protected]> Date: Sat May 9 06:04:48 2026 +0900 xtensa: Define HONOR_REG_ALLOC_ORDER as 1 Since the commit of the preceding patch for IRA, "ira: Scale save/restore costs of callee save registers with block frequency" (3b9b8d6cfdf59337f4b7ce10ce92a98044b2657b), the Xtensa ISA has shown a tendency to allocate slightly more function stack frames, especially when using the CALL0 ABI. /* example */ extern void foo(void); int test(int a) { int array[252]; foo(); asm volatile (""::"m"(array)); return a; } ;; before (-O2 -mabi=call0) test: addi sp, sp, -16 s32i.n a0, sp, 12 addmi sp, sp, -0x400 s32i a2, sp, 1008 call0 foo l32i a2, sp, 1008 addmi sp, sp, 0x400 l32i.n a0, sp, 12 addi sp, sp, 16 ret.n This patch disables the incorrect register save cost estimation in function prologues/epilogues by defining the HONOR_REG_ALLOC_ORDER macro as 1. ;; after (-O2 -mabi=call0) test: addmi sp, sp, -0x400 s32i a0, sp, 1020 s32i a2, sp, 1016 call0 foo l32i a2, sp, 1016 l32i a0, sp, 1020 addmi sp, sp, 0x400 ret.n gcc/ChangeLog: * config/xtensa/xtensa.h (HONOR_REG_ALLOC_ORDER): New macro definition. gcc/testsuite/ChangeLog: * gcc.target/xtensa/elim_callee_saved.c: Revise the test item for the number of mov instructions in the assembler output. Diff: --- gcc/config/xtensa/xtensa.h | 4 ++++ gcc/testsuite/gcc.target/xtensa/elim_callee_saved.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h index 2bf43f7af42c..3b33d69bf210 100644 --- a/gcc/config/xtensa/xtensa.h +++ b/gcc/config/xtensa/xtensa.h @@ -254,6 +254,10 @@ along with GCC; see the file COPYING3. If not see } #define ADJUST_REG_ALLOC_ORDER xtensa_adjust_reg_alloc_order () +/* Tell IRA to use the order we define rather than messing it up with its + own cost calculations. */ +#define HONOR_REG_ALLOC_ORDER 1 + /* Internal macros to classify a register number. */ /* 16 address registers + fake registers */ diff --git a/gcc/testsuite/gcc.target/xtensa/elim_callee_saved.c b/gcc/testsuite/gcc.target/xtensa/elim_callee_saved.c index cd3d6b9f2496..69e5be35dfd0 100644 --- a/gcc/testsuite/gcc.target/xtensa/elim_callee_saved.c +++ b/gcc/testsuite/gcc.target/xtensa/elim_callee_saved.c @@ -34,5 +34,5 @@ int __attribute__((optimize(0))) test3(int a) { return bar() + a; } -/* { dg-final { scan-assembler-times "mov\t|mov.n\t" 21 } } */ +/* { dg-final { scan-assembler-times "mov\t|mov.n\t" 20 } } */ /* { dg-final { scan-assembler-times "a15, 8" 2 } } */
