https://gcc.gnu.org/g:3c6318c5ecbccbbfa76e90f97c69e6aa74bf7c5d
commit r17-490-g3c6318c5ecbccbbfa76e90f97c69e6aa74bf7c5d Author: Jeevitha <[email protected]> Date: Wed May 13 03:36:10 2026 -0500 rs6000: Fix [su]mul<mode>3_highpart patterns to use RTL codes [PR122665] The existing smul<mode>3_highpart and umul<mode>3_highpart patterns incorrectly defined the high-part multiply by shifting both operands right by 32 before multiplication. This does not match the semantics of the instructions vmulhs<wd> and vmulhu<wd>, which perform a widened multiplication and return the high part of the result. This patch replaces the incorrect shift-based patterns with the proper smul_highpart and umul_highpart RTL codes, and updates the operand predicate from vsx_register_operand to altivec_register_operand, since these instructions only accept Altivec registers. 2026-05-13 Jeevitha Palanisamy <[email protected]> gcc/ PR target/122665 * config/rs6000/vsx.md (smul<mode>3_highpart, umul<mode>3_highpart): Replace shift-based patterns with smul_highpart and umul_highpart RTL codes and use altivec_register_operand. Diff: --- gcc/config/rs6000/vsx.md | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index cfad9b8c6d54..f5ace28ea93a 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -6547,25 +6547,19 @@ (set_attr "size" "<bits>")]) (define_insn "smul<mode>3_highpart" - [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") - (mult:VIlong (ashiftrt - (match_operand:VIlong 1 "vsx_register_operand" "v") - (const_int 32)) - (ashiftrt - (match_operand:VIlong 2 "vsx_register_operand" "v") - (const_int 32))))] + [(set (match_operand:VIlong 0 "altivec_register_operand" "=v") + (smul_highpart:VIlong + (match_operand:VIlong 1 "altivec_register_operand" "v") + (match_operand:VIlong 2 "altivec_register_operand" "v")))] "TARGET_POWER10" "vmulhs<wd> %0,%1,%2" [(set_attr "type" "veccomplex")]) (define_insn "umul<mode>3_highpart" - [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") - (us_mult:VIlong (ashiftrt - (match_operand:VIlong 1 "vsx_register_operand" "v") - (const_int 32)) - (ashiftrt - (match_operand:VIlong 2 "vsx_register_operand" "v") - (const_int 32))))] + [(set (match_operand:VIlong 0 "altivec_register_operand" "=v") + (umul_highpart:VIlong + (match_operand:VIlong 1 "altivec_register_operand" "v") + (match_operand:VIlong 2 "altivec_register_operand" "v")))] "TARGET_POWER10" "vmulhu<wd> %0,%1,%2" [(set_attr "type" "veccomplex")])
