https://gcc.gnu.org/g:5386f141f0cb0abb01201a28e45ff3807973a5cc
commit r17-969-g5386f141f0cb0abb01201a28e45ff3807973a5cc Author: Artemiy Volkov <[email protected]> Date: Thu Mar 12 12:19:29 2026 +0000 aarch64: add preliminary definitions for SVE2.2/SME2.2 This is a preparatory patch for the bulk of the SVE2.2/SME2.2 support series, putting into place some machinery used by the later patches. This includes TARGET_* constants that are set based on ISA flags, and new match_test definitions that are used to enable/disable individual instruction patterns/alternatives. On the testsuite side of things, this patch adds two new effective-target checks in lib/target-supports.exp, one for each of SVE2.2-capable HW and toolchain. v1 of this patch also contained __ARM_FEATURE_* macro definitions for SVE2.2 and SME2.2, but these have been moved to the end of the series to improve bisection. gcc/ChangeLog: * config/aarch64/aarch64.h (TARGET_SVE2p2): New macro. (TARGET_SME2p2): Likewise. (TARGET_SVE2p2_OR_SME2p2): Likewise. * config/aarch64/aarch64.md (arches): Add sve2p2_or_sme2p2 enum constant. (arch): Add test for sve2p2_or_sme2p2. * doc/invoke.texi: Document sve2p2 and sme2p2 extensions. gcc/testsuite/ChangeLog: * lib/target-supports.exp (check_effective_target_aarch64_sve2p2_hw): New target check. (check_effective_target_aarch64_sve2p2_ok): New target check. (exts_sve2): Add sme2p2. Diff: --- gcc/config/aarch64/aarch64.h | 10 ++++++++++ gcc/config/aarch64/aarch64.md | 7 +++++-- gcc/doc/invoke.texi | 5 +++++ gcc/testsuite/lib/target-supports.exp | 29 ++++++++++++++++++++++++++++- 4 files changed, 48 insertions(+), 3 deletions(-) diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 681dff03bbf0..1f6284e40f1a 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -313,6 +313,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED /* SVE2p1 instructions, enabled through +sve2p1. */ #define TARGET_SVE2p1 AARCH64_HAVE_ISA (SVE2p1) +/* SVE2p2 instructions, enabled through +sve2p2. */ +#define TARGET_SVE2p2 AARCH64_HAVE_ISA (SVE2p2) + /* SME instructions, enabled through +sme. Note that this does not imply anything about the state of PSTATE.SM; instructions that require SME and streaming mode should use TARGET_STREAMING instead. */ @@ -343,6 +346,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED /* SME2 instructions, enabled through +sme2. */ #define TARGET_SME2 AARCH64_HAVE_ISA (SME2) +/* SME2p2 instructions, enabled through +sme2p2. */ +#define TARGET_SME2p2 AARCH64_HAVE_ISA (SME2p2) + /* Same with streaming mode enabled. */ #define TARGET_STREAMING_SME2 (TARGET_STREAMING && TARGET_SME2) @@ -522,6 +528,10 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED ((TARGET_SVE2p1 || TARGET_STREAMING) \ && (TARGET_SME2 || TARGET_NON_STREAMING)) +#define TARGET_SVE2p2_OR_SME2p2 \ + ((TARGET_SVE2p2 || TARGET_STREAMING) \ + && (TARGET_SME2p2 || TARGET_NON_STREAMING)) + #define TARGET_SSVE_B16B16 \ (AARCH64_HAVE_ISA (SVE_B16B16) && TARGET_SVE2_OR_SME2) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 595cc14c85ab..8cf26446006c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -502,7 +502,7 @@ ;; Q registers and is equivalent to "simd". (define_enum "arches" [any rcpc8_4 fp fp_q base_simd nobase_simd - simd nosimd sve fp16 sme cssc]) + simd nosimd sve fp16 sme cssc sve2p2_or_sme2p2]) (define_enum_attr "arch" "arches" (const_string "any")) @@ -581,7 +581,10 @@ (match_test "TARGET_SVE")) (and (eq_attr "arch" "sme") - (match_test "TARGET_SME")))) + (match_test "TARGET_SME")) + + (and (eq_attr "arch" "sve2p2_or_sme2p2") + (match_test "TARGET_SVE2p2_OR_SME2p2")))) (const_string "yes") (const_string "no"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 8ed1c851f598..5374cbbfb6f5 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21966,6 +21966,8 @@ Enable SVE2 aes instructions. This also enables SVE2 instructions. Enable SVE2 sha3 instructions. This also enables SVE2 instructions. @item sve2p1 Enable SVE2.1 instructions. This also enables SVE2 instructions. +@item sve2p2 +Enable SVE2.2 instructions. This also enables SVE2 and SVE2.1 instructions. @item tme Enable the Transactional Memory Extension. @item i8mm @@ -22028,6 +22030,9 @@ instructions. @item sme2p1 Enable the Scalable Matrix Extension version 2.1. This also enables SME2 instructions. +@item sme2p2 +Enable the Scalable Matrix Extension version 2.2. This also enables SME2 +and SME2.1 instructions. @item fcma Enable the complex number SIMD extensions. @item jscvt diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index d1fcf943b211..ca79080629f5 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -6710,6 +6710,23 @@ proc check_effective_target_aarch64_sve2p1_hw { } { }] } +# Return true if this is an AArch64 target that can run SVE2.2 code. + +proc check_effective_target_aarch64_sve2p2_hw { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_runtime aarch64_sve2p2_hw_available { + #pragma GCC target "+sve2p2" + int + main (void) + { + asm volatile ("compact z0.b, p0, z1.b"); + return 0; + } + }] +} + # Return true if this is an AArch64 target that can run SVE code and # if its SVE vectors have exactly BITS bits. @@ -12772,7 +12789,7 @@ set exts { "sb" "simd" "sve-b16b16" "sve" "sve2" "sve-sm4" "sve-aes" "sve-bitperm" "sve-sha3" "f8f16mm" "f8f32mm" "sve-f16f32mm" "sme-f8f16" "sme-f8f32" - "sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1" + "sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1" "sme2p2" "ssve-fp8dot2" "ssve-fp8dot4" "ssve-fp8fma" "sve-bfscale" "sme-lutv2" } @@ -12810,6 +12827,16 @@ proc check_effective_target_aarch64_asm_sve2p1_ok { } { } } +proc check_effective_target_aarch64_asm_sve2p2_ok { } { + if { [istarget aarch64*-*-*] } { + return [check_no_compiler_messages aarch64_sve2p2_assembler object { + __asm__ (".arch_extension sve2p2; compact z0.b,p0,z1.b"); + } "-march=armv8-a+sve2p2"] + } else { + return 0 + } +} + proc check_effective_target_aarch64_small { } { if { [istarget aarch64*-*-*] } { return [check_no_compiler_messages aarch64_small object {
