https://gcc.gnu.org/g:0a27a52771edd1a59b5e342a9e732f81b5395176
commit r17-977-g0a27a52771edd1a59b5e342a9e732f81b5395176 Author: Artemiy Volkov <[email protected]> Date: Thu Dec 11 11:17:46 2025 +0000 aarch64: implement FRINT32/64 SVE instructions SVE2.2 (or in streaming mode, SME2.2) adds the following SVE instructions: - FRINT32X (Floating-point round to 32-bit integer (predicated)) - FRINT32Z (Floating-point round to 32-bit integer, rounding toward zero (predicated)) - FRINT64X (Floating-point round to 64-bit integer (predicated)) - FRINT64Z (Floating-point round to 64-bit integer, rounding toward zero (predicated)) The intrinsics that expand to them are defined in the ACLE manual [0]: svfloat{32,64}_t svrint32x{_f32,_f64}_z (svbool_t pg, svfloat{32,64}_t zn); svfloat{32,64}_t svrint32x{_f32,_f64}_x (svbool_t pg, svfloat{32,64}_t zn); svfloat{32,64}_t svrint32x{_f32,_f64}_m (svfloat{32,64}_t inactive, svbool_t pg, svfloat{32,64}_t zn); svfloat{32,64}_t svrint32z{_f32,_f64}_z (svbool_t pg, svfloat{32,64}_t zn); svfloat{32,64}_t svrint32z{_f32,_f64}_x (svbool_t pg, svfloat{32,64}_t zn); svfloat{32,64}_t svrint32z{_f32,_f64}_m (svfloat{32,64}_t inactive, svbool_t pg, svfloat{32,64}_t zn); svfloat{32,64}_t svrint64x{_f32,_f64}_z (svbool_t pg, svfloat{32,64}_t zn); svfloat{32,64}_t svrint64x{_f32,_f64}_x (svbool_t pg, svfloat{32,64}_t zn); svfloat{32,64}_t svrint64x{_f32,_f64}_m (svfloat{32,64}_t inactive, svbool_t pg, svfloat{32,64}_t zn); svfloat{32,64}_t svrint64z{_f32,_f64}_z (svbool_t pg, svfloat{32,64}_t zn); svfloat{32,64}_t svrint64z{_f32,_f64}_x (svbool_t pg, svfloat{32,64}_t zn); svfloat{32,64}_t svrint64z{_f32,_f64}_m (svfloat{32,64}_t inactive, svbool_t pg, svfloat{32,64}_t zn); The implementation of new intrinsics and RTL patterns is quite straightforward, and a standard set of ASM tests has been added to the sve2/acle/asm directory. [0] https://github.com/ARM-software/acle Changes since v1: - Append extension names to comments in aarch64-sve2.md. gcc/ChangeLog: * config/aarch64/aarch64-sve-builtins-sve2.cc (svrint32x): Define new function base. (svrint32z): Likewise. (svrint64x): Likewise. (svrint64z): Likewise. * config/aarch64/aarch64-sve-builtins-sve2.def (svrint32x): Define new SVE function. (svrint32z): Likewise. (svrint64x): Likewise. (svrint64z): Likewise. * config/aarch64/aarch64-sve-builtins-sve2.h (svrint32x): Declare new function base. (svrint32z): Likewise. (svrint64x): Likewise. (svrint32z): Likewise. * config/aarch64/aarch64-sve-builtins.cc (TYPES_sd_float): New type set. (sd_float): New SVE type array. * config/aarch64/aarch64-sve2.md (@cond_<frintnzs_op><mode>): New insn pattern. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve2/acle/asm/rint32x_f32.c: New test. * gcc.target/aarch64/sve2/acle/asm/rint32x_f64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rint32z_f32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rint32z_f64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rint64x_f32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rint64x_f64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rint64z_f32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rint64z_f64.c: Likewise. Diff: --- gcc/config/aarch64/aarch64-sve-builtins-sve2.cc | 4 ++ gcc/config/aarch64/aarch64-sve-builtins-sve2.def | 4 ++ gcc/config/aarch64/aarch64-sve-builtins-sve2.h | 4 ++ gcc/config/aarch64/aarch64-sve-builtins.cc | 5 ++ gcc/config/aarch64/aarch64-sve2.md | 29 +++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rint32x_f32.c | 59 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rint32x_f64.c | 59 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rint32z_f32.c | 59 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rint32z_f64.c | 59 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rint64x_f32.c | 59 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rint64x_f64.c | 59 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rint64z_f32.c | 59 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rint64z_f64.c | 59 ++++++++++++++++++++++ 13 files changed, 518 insertions(+) diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc index 86ea2efe5aa5..d45012e79362 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc @@ -1186,6 +1186,10 @@ FUNCTION (svrax1, fixed_insn_function, (CODE_FOR_aarch64_sve2_rax1)) FUNCTION (svrevd, unspec_based_function, (UNSPEC_REVD, UNSPEC_REVD, UNSPEC_REVD)) FUNCTION (svrhadd, unspec_based_function, (UNSPEC_SRHADD, UNSPEC_URHADD, -1)) +FUNCTION (svrint32x, unspec_based_function, (-1, -1, UNSPEC_FRINT32X)) +FUNCTION (svrint32z, unspec_based_function, (-1, -1, UNSPEC_FRINT32Z)) +FUNCTION (svrint64x, unspec_based_function, (-1, -1, UNSPEC_FRINT64X)) +FUNCTION (svrint64z, unspec_based_function, (-1, -1, UNSPEC_FRINT64Z)) FUNCTION (svrshl, svrshl_impl,) FUNCTION (svrshr, unspec_based_function, (UNSPEC_SRSHR, UNSPEC_URSHR, -1)) FUNCTION (svrshrnb, unspec_based_function, (UNSPEC_RSHRNB, UNSPEC_RSHRNB, -1)) diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def index 82714361275a..f93c26e7d848 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def @@ -304,6 +304,10 @@ DEF_SVE_FUNCTION (svcvtlt, unary_convert, cvt_long, z) DEF_SVE_FUNCTION (svcvtnt, unary_convert_narrowt, cvt_narrow, z) DEF_SVE_FUNCTION (svcvtnt, unary_convert_narrowt, cvt_bfloat, z) DEF_SVE_FUNCTION (svcvtxnt, unary_convert_narrowt, cvt_narrow_s, z) +DEF_SVE_FUNCTION (svrint32x, unary, sd_float, mxz) +DEF_SVE_FUNCTION (svrint32z, unary, sd_float, mxz) +DEF_SVE_FUNCTION (svrint64x, unary, sd_float, mxz) +DEF_SVE_FUNCTION (svrint64z, unary, sd_float, mxz) #undef REQUIRED_EXTENSIONS #define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2) diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h index f191f47cbabf..8b1581f8568b 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h @@ -196,6 +196,10 @@ namespace aarch64_sve extern const function_base *const svrax1; extern const function_base *const svrevd; extern const function_base *const svrhadd; + extern const function_base *const svrint32x; + extern const function_base *const svrint32z; + extern const function_base *const svrint64x; + extern const function_base *const svrint64z; extern const function_base *const svrshl; extern const function_base *const svrshr; extern const function_base *const svrshrnb; diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc b/gcc/config/aarch64/aarch64-sve-builtins.cc index d25e5437ba82..99acd13edf84 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins.cc @@ -209,6 +209,10 @@ CONSTEXPR const group_suffix_info group_suffixes[] = { #define TYPES_all_float(S, D, T) \ S (f16), S (f32), S (f64) +/* _f32 _f64. */ +#define TYPES_sd_float(S, D, T) \ + S (f32), S (f64) + /* _s8 _s16 _s32 _s64. */ #define TYPES_all_signed(S, D, T) \ S (s8), S (s16), S (s32), S (s64) @@ -830,6 +834,7 @@ DEF_SVE_TYPES_ARRAY (s_signed); DEF_SVE_TYPES_ARRAY (s_unsigned); DEF_SVE_TYPES_ARRAY (s_integer); DEF_SVE_TYPES_ARRAY (s_data); +DEF_SVE_TYPES_ARRAY (sd_float); DEF_SVE_TYPES_ARRAY (sd_signed); DEF_SVE_TYPES_ARRAY (sd_unsigned); DEF_SVE_TYPES_ARRAY (sd_integer); diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 97beccbe51f7..b56b909741cd 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -48,6 +48,7 @@ ;; ---- [PRED] Predicate count ;; ;; == Uniform unary arithmnetic +;; ---- [FP] General unary arithmetic that maps to unspecs ;; ---- [FP] Multi-register unary operations ;; ;; == Uniform binary arithmnetic @@ -724,6 +725,34 @@ ;; == Uniform unary arithmnetic ;; ========================================================================= +;; ------------------------------------------------------------------------- +;; ---- [FP] General unary arithmetic that maps to unspecs +;; ------------------------------------------------------------------------- +;; Includes: +;; - FRINT32X (SVE2p2, SME2p2) +;; - FRINT32Z (SVE2p2, SME2p2) +;; - FRINT64X (SVE2p2, SME2p2) +;; - FRINT64Z (SVE2p2, SME2p2) +;; ------------------------------------------------------------------------- + +(define_insn "@cond_<frintnzs_op><mode>" + [(set (match_operand:SVE_FULL_SDF 0 "register_operand") + (unspec:SVE_FULL_SDF + [(match_operand:<VPRED> 1 "register_operand") + (unspec:SVE_FULL_SDF + [(match_operand:SVE_FULL_SDF 2 "register_operand")] + FRINTNZX) + (match_operand:SVE_FULL_SDF 3 "aarch64_simd_reg_or_zero")] + UNSPEC_SEL))] + "TARGET_SVE2p2_OR_SME2p2" + {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ] + [ w , Upl , w , 0 ; * ] <frintnzs_op>\t%0.<SVE_FULL_SDF:Vetype>, %1/m, %2.<SVE_FULL_SDF:Vetype> + [ w , Upl , w , Dz ; * ] <frintnzs_op>\t%0.<SVE_FULL_SDF:Vetype>, %1/z, %2.<SVE_FULL_SDF:Vetype> + [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;<frintnzs_op>\t%0.<SVE_FULL_SDF:Vetype>, %1/m, %2.<SVE_FULL_SDF:Vetype> + } + [(set_attr "sve_type" "sve_fp_cvt")] +) + ;; ------------------------------------------------------------------------- ;; ---- [FP] Multi-register unary operations ;; ------------------------------------------------------------------------- diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint32x_f32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint32x_f32.c new file mode 100644 index 000000000000..eca4913c7ab0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint32x_f32.c @@ -0,0 +1,59 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rint32x_f32_m_tied1: +** frint32x z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (rint32x_f32_m_tied1, svfloat32_t, svfloat32_t, + z0 = svrint32x_f32_m (z0, p0, z4), + z0 = svrint32x_m (z0, p0, z4)) + +/* +** rint32x_f32_m_untied: +** movprfx z0, z1 +** frint32x z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (rint32x_f32_m_untied, svfloat32_t, svfloat32_t, + z0 = svrint32x_f32_m (z1, p0, z4), + z0 = svrint32x_m (z1, p0, z4)) + +/* +** rint32x_f32_z: +** frint32x z0\.s, p0/z, z4\.s +** ret +*/ +TEST_DUAL_Z (rint32x_f32_z, svfloat32_t, svfloat32_t, + z0 = svrint32x_f32_z (p0, z4), + z0 = svrint32x_z (p0, z4)) + +/* +** rint32x_f32_x: +** movprfx z0, z4 +** frint32x z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (rint32x_f32_x, svfloat32_t, svfloat32_t, + z0 = svrint32x_f32_x (p0, z4), + z0 = svrint32x_x (p0, z4)) + +/* +** ptrue_rint32x_f32_x: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_rint32x_f32_x, svfloat32_t, svfloat32_t, + z0 = svrint32x_f32_x (svptrue_b32 (), z4), + z0 = svrint32x_x (svptrue_b32 (), z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint32x_f64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint32x_f64.c new file mode 100644 index 000000000000..83958c95e574 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint32x_f64.c @@ -0,0 +1,59 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rint32x_f64_m_tied1: +** frint32x z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (rint32x_f64_m_tied1, svfloat64_t, svfloat64_t, + z0 = svrint32x_f64_m (z0, p0, z4), + z0 = svrint32x_m (z0, p0, z4)) + +/* +** rint32x_f64_m_untied: +** movprfx z0, z1 +** frint32x z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (rint32x_f64_m_untied, svfloat64_t, svfloat64_t, + z0 = svrint32x_f64_m (z1, p0, z4), + z0 = svrint32x_m (z1, p0, z4)) + +/* +** rint32x_f64_z: +** frint32x z0\.d, p0/z, z4\.d +** ret +*/ +TEST_DUAL_Z (rint32x_f64_z, svfloat64_t, svfloat64_t, + z0 = svrint32x_f64_z (p0, z4), + z0 = svrint32x_z (p0, z4)) + +/* +** rint32x_f64_x: +** movprfx z0, z4 +** frint32x z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (rint32x_f64_x, svfloat64_t, svfloat64_t, + z0 = svrint32x_f64_x (p0, z4), + z0 = svrint32x_x (p0, z4)) + +/* +** ptrue_rint32x_f64_x: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_rint32x_f64_x, svfloat64_t, svfloat64_t, + z0 = svrint32x_f64_x (svptrue_b64 (), z4), + z0 = svrint32x_x (svptrue_b64 (), z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint32z_f32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint32z_f32.c new file mode 100644 index 000000000000..656fc2f7cac7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint32z_f32.c @@ -0,0 +1,59 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rint32z_f32_m_tied1: +** frint32z z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (rint32z_f32_m_tied1, svfloat32_t, svfloat32_t, + z0 = svrint32z_f32_m (z0, p0, z4), + z0 = svrint32z_m (z0, p0, z4)) + +/* +** rint32z_f32_m_untied: +** movprfx z0, z1 +** frint32z z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (rint32z_f32_m_untied, svfloat32_t, svfloat32_t, + z0 = svrint32z_f32_m (z1, p0, z4), + z0 = svrint32z_m (z1, p0, z4)) + +/* +** rint32z_f32_z: +** frint32z z0\.s, p0/z, z4\.s +** ret +*/ +TEST_DUAL_Z (rint32z_f32_z, svfloat32_t, svfloat32_t, + z0 = svrint32z_f32_z (p0, z4), + z0 = svrint32z_z (p0, z4)) + +/* +** rint32z_f32_x: +** movprfx z0, z4 +** frint32z z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (rint32z_f32_x, svfloat32_t, svfloat32_t, + z0 = svrint32z_f32_x (p0, z4), + z0 = svrint32z_x (p0, z4)) + +/* +** ptrue_rint32z_f32_x: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_rint32z_f32_x, svfloat32_t, svfloat32_t, + z0 = svrint32z_f32_x (svptrue_b32 (), z4), + z0 = svrint32z_x (svptrue_b32 (), z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint32z_f64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint32z_f64.c new file mode 100644 index 000000000000..0cb06a33f1ea --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint32z_f64.c @@ -0,0 +1,59 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rint32z_f64_m_tied1: +** frint32z z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (rint32z_f64_m_tied1, svfloat64_t, svfloat64_t, + z0 = svrint32z_f64_m (z0, p0, z4), + z0 = svrint32z_m (z0, p0, z4)) + +/* +** rint32z_f64_m_untied: +** movprfx z0, z1 +** frint32z z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (rint32z_f64_m_untied, svfloat64_t, svfloat64_t, + z0 = svrint32z_f64_m (z1, p0, z4), + z0 = svrint32z_m (z1, p0, z4)) + +/* +** rint32z_f64_z: +** frint32z z0\.d, p0/z, z4\.d +** ret +*/ +TEST_DUAL_Z (rint32z_f64_z, svfloat64_t, svfloat64_t, + z0 = svrint32z_f64_z (p0, z4), + z0 = svrint32z_z (p0, z4)) + +/* +** rint32z_f64_x: +** movprfx z0, z4 +** frint32z z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (rint32z_f64_x, svfloat64_t, svfloat64_t, + z0 = svrint32z_f64_x (p0, z4), + z0 = svrint32z_x (p0, z4)) + +/* +** ptrue_rint32z_f64_x: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_rint32z_f64_x, svfloat64_t, svfloat64_t, + z0 = svrint32z_f64_x (svptrue_b64 (), z4), + z0 = svrint32z_x (svptrue_b64 (), z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint64x_f32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint64x_f32.c new file mode 100644 index 000000000000..b9139507147a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint64x_f32.c @@ -0,0 +1,59 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rint64x_f32_m_tied1: +** frint64x z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (rint64x_f32_m_tied1, svfloat32_t, svfloat32_t, + z0 = svrint64x_f32_m (z0, p0, z4), + z0 = svrint64x_m (z0, p0, z4)) + +/* +** rint64x_f32_m_untied: +** movprfx z0, z1 +** frint64x z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (rint64x_f32_m_untied, svfloat32_t, svfloat32_t, + z0 = svrint64x_f32_m (z1, p0, z4), + z0 = svrint64x_m (z1, p0, z4)) + +/* +** rint64x_f32_z: +** frint64x z0\.s, p0/z, z4\.s +** ret +*/ +TEST_DUAL_Z (rint64x_f32_z, svfloat32_t, svfloat32_t, + z0 = svrint64x_f32_z (p0, z4), + z0 = svrint64x_z (p0, z4)) + +/* +** rint64x_f32_x: +** movprfx z0, z4 +** frint64x z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (rint64x_f32_x, svfloat32_t, svfloat32_t, + z0 = svrint64x_f32_x (p0, z4), + z0 = svrint64x_x (p0, z4)) + +/* +** ptrue_rint64x_f32_x: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_rint64x_f32_x, svfloat32_t, svfloat32_t, + z0 = svrint64x_f32_x (svptrue_b32 (), z4), + z0 = svrint64x_x (svptrue_b32 (), z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint64x_f64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint64x_f64.c new file mode 100644 index 000000000000..37f1bf78b789 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint64x_f64.c @@ -0,0 +1,59 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rint64x_f64_m_tied1: +** frint64x z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (rint64x_f64_m_tied1, svfloat64_t, svfloat64_t, + z0 = svrint64x_f64_m (z0, p0, z4), + z0 = svrint64x_m (z0, p0, z4)) + +/* +** rint64x_f64_m_untied: +** movprfx z0, z1 +** frint64x z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (rint64x_f64_m_untied, svfloat64_t, svfloat64_t, + z0 = svrint64x_f64_m (z1, p0, z4), + z0 = svrint64x_m (z1, p0, z4)) + +/* +** rint64x_f64_z: +** frint64x z0\.d, p0/z, z4\.d +** ret +*/ +TEST_DUAL_Z (rint64x_f64_z, svfloat64_t, svfloat64_t, + z0 = svrint64x_f64_z (p0, z4), + z0 = svrint64x_z (p0, z4)) + +/* +** rint64x_f64_x: +** movprfx z0, z4 +** frint64x z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (rint64x_f64_x, svfloat64_t, svfloat64_t, + z0 = svrint64x_f64_x (p0, z4), + z0 = svrint64x_x (p0, z4)) + +/* +** ptrue_rint64x_f64_x: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_rint64x_f64_x, svfloat64_t, svfloat64_t, + z0 = svrint64x_f64_x (svptrue_b64 (), z4), + z0 = svrint64x_x (svptrue_b64 (), z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint64z_f32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint64z_f32.c new file mode 100644 index 000000000000..ef2b31212f80 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint64z_f32.c @@ -0,0 +1,59 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rint64z_f32_m_tied1: +** frint64z z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (rint64z_f32_m_tied1, svfloat32_t, svfloat32_t, + z0 = svrint64z_f32_m (z0, p0, z4), + z0 = svrint64z_m (z0, p0, z4)) + +/* +** rint64z_f32_m_untied: +** movprfx z0, z1 +** frint64z z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (rint64z_f32_m_untied, svfloat32_t, svfloat32_t, + z0 = svrint64z_f32_m (z1, p0, z4), + z0 = svrint64z_m (z1, p0, z4)) + +/* +** rint64z_f32_z: +** frint64z z0\.s, p0/z, z4\.s +** ret +*/ +TEST_DUAL_Z (rint64z_f32_z, svfloat32_t, svfloat32_t, + z0 = svrint64z_f32_z (p0, z4), + z0 = svrint64z_z (p0, z4)) + +/* +** rint64z_f32_x: +** movprfx z0, z4 +** frint64z z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (rint64z_f32_x, svfloat32_t, svfloat32_t, + z0 = svrint64z_f32_x (p0, z4), + z0 = svrint64z_x (p0, z4)) + +/* +** ptrue_rint64z_f32_x: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_rint64z_f32_x, svfloat32_t, svfloat32_t, + z0 = svrint64z_f32_x (svptrue_b32 (), z4), + z0 = svrint64z_x (svptrue_b32 (), z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint64z_f64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint64z_f64.c new file mode 100644 index 000000000000..d79145273f27 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rint64z_f64.c @@ -0,0 +1,59 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rint64z_f64_m_tied1: +** frint64z z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (rint64z_f64_m_tied1, svfloat64_t, svfloat64_t, + z0 = svrint64z_f64_m (z0, p0, z4), + z0 = svrint64z_m (z0, p0, z4)) + +/* +** rint64z_f64_m_untied: +** movprfx z0, z1 +** frint64z z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (rint64z_f64_m_untied, svfloat64_t, svfloat64_t, + z0 = svrint64z_f64_m (z1, p0, z4), + z0 = svrint64z_m (z1, p0, z4)) + +/* +** rint64z_f64_z: +** frint64z z0\.d, p0/z, z4\.d +** ret +*/ +TEST_DUAL_Z (rint64z_f64_z, svfloat64_t, svfloat64_t, + z0 = svrint64z_f64_z (p0, z4), + z0 = svrint64z_z (p0, z4)) + +/* +** rint64z_f64_x: +** movprfx z0, z4 +** frint64z z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (rint64z_f64_x, svfloat64_t, svfloat64_t, + z0 = svrint64z_f64_x (p0, z4), + z0 = svrint64z_x (p0, z4)) + +/* +** ptrue_rint64z_f64_x: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_rint64z_f64_x, svfloat64_t, svfloat64_t, + z0 = svrint64z_f64_x (svptrue_b64 (), z4), + z0 = svrint64z_x (svptrue_b64 (), z4))
