https://gcc.gnu.org/g:311b1afe7e459fabaf6e3b80322437173b69846f
commit r17-1096-g311b1afe7e459fabaf6e3b80322437173b69846f Author: Dhruv Chawla <[email protected]> Date: Tue May 19 12:53:37 2026 +0000 avr: Fix typos in various files Signed-off-by: Dhruv Chawla <[email protected]> gcc/ChangeLog: * common/config/avr/avr-common.cc: Fix typos. * config/avr/avr-passes.cc (size_to_mode): Likewise. (struct absint_t): Likewise. (plies_t::emit_sets): Likewise. (avr_strict_unsigned_p): Likewise. (avr_redundant_compare): Likewise. (avr_optimize_casesi): Likewise. (struct AVR_LdSt_Props): Likewise. (avr_pass_split_nzb::split_nzb_insns): Likewise. (make_avr_pass_fuse_move): Likewise. * config/avr/avr.cc (avr_option_override): Likewise. (avr_can_inline_p): Likewise. (avr_expand_epilogue): Likewise. (avr_init_cumulative_args): Likewise. (reg_unused_after): Likewise. (avr_out_lpm_no_lpmx): Likewise. (avr_out_compare): Likewise. (avr_out_plus_ext): Likewise. (avr_out_fract): Likewise. (avr_nonzero_bits_lsr_operands_p): Likewise. * config/avr/avr.h (avr_no_devlib): Likewise. (struct machine_function): Likewise. * config/avr/avr.md: Likewise. * config/avr/builtins.def (FLASH_SEGMENT): Likewise. * config/avr/specs.h: Likewise. libgcc/config/avr/libf7/ChangeLog: * libf7.c (f7_addsub): Likewise. (f7_madd_msub): Likewise. * libf7.h (f7_Ildexp): Likewise. Diff: --- gcc/common/config/avr/avr-common.cc | 2 +- gcc/config/avr/avr-passes.cc | 18 +++++++++--------- gcc/config/avr/avr.cc | 20 ++++++++++---------- gcc/config/avr/avr.h | 4 ++-- gcc/config/avr/avr.md | 12 ++++++------ gcc/config/avr/builtins.def | 4 ++-- gcc/config/avr/specs.h | 2 +- libgcc/config/avr/libf7/libf7.c | 4 ++-- libgcc/config/avr/libf7/libf7.h | 2 +- 9 files changed, 34 insertions(+), 34 deletions(-) diff --git a/gcc/common/config/avr/avr-common.cc b/gcc/common/config/avr/avr-common.cc index 0792bfee593c..8d1923a72bf3 100644 --- a/gcc/common/config/avr/avr-common.cc +++ b/gcc/common/config/avr/avr-common.cc @@ -30,7 +30,7 @@ static const struct default_options avr_option_optimization_table[] = { // There is no way to filter out unwanted cswtch transformations: - // - Code bload as mentioned in PR81540. + // - Code bloat as mentioned in PR81540. // - When tree-switch-conversion.cc::build_one_array() finds a // linear function, it will use a formula that involves a // multiplication without even trying to work out the costs. diff --git a/gcc/config/avr/avr-passes.cc b/gcc/config/avr/avr-passes.cc index ec21fed4eb83..5ade9971806f 100644 --- a/gcc/config/avr/avr-passes.cc +++ b/gcc/config/avr/avr-passes.cc @@ -403,7 +403,7 @@ static machine_mode size_to_mode (int size) Each insn is optimized on its own, or may be fused with the previous insn like in example (1). As the insns are traversed, memento_t keeps track of known values - held in the GPRs (general purpse registers) R2 ... R31 by simulating + held in the GPRs (general purpose registers) R2 ... R31 by simulating the effect of the current insn in memento_t.apply_insn(). The basic blocks are traversed in reverse post order so as to maximize the chance that GPRs from all preceding blocks are known, @@ -480,7 +480,7 @@ struct absint_t; // A ply_t is a potential step towards an optimal sequence to load a constant // value into a multi-byte register. A ply_t loosely relates to one AVR // instruction, but it may also represent a sequence of instructions. -// For example, loading a constant into a lower register when no sratch reg +// For example, loading a constant into a lower register when no scratch reg // is available may take up to 4 instructions. There is no 1:1 correspondence // to insns, either. // try_split_ldi determines the best sequence of ply_t's by means of a @@ -1578,7 +1578,7 @@ plies_t::emit_sets (const insninfo_t &ii, int &n_insns, const memento_t &memo, // Try to find an operation such that Y = op (X). -// Shifts and rotates are regarded as unary operaions with +// Shifts and rotates are regarded as unary operations with // an implied 2nd operand or 1 or 4, respectively. static rtx_code find_arith (uint8_t y, uint8_t x) @@ -3364,7 +3364,7 @@ avr_strict_unsigned_p (rtx_code code) then set CMP1 = cond1, CMP2 = cond2, and return xval. Else return NULL_RTX. When SWAPT is returned true, then way1 and way2 must be swapped. - When the incomping SWAPT is false, the outgoing one will be false, too. */ + When the incoming SWAPT is false, the outgoing one will be false, too. */ static rtx avr_2comparisons_rhs (rtx_code &cmp1, rtx xval1, @@ -3600,7 +3600,7 @@ avr_redundant_compare (rtx xreg1, rtx_code &cond1, rtx xval1, if (REG_CC <cmp2> 0) goto label2; then set XREG1 to reg, COND1 and COND2 accordingly, and return xval. - Otherwise, return NULL_RTX. This optmization can be performed + Otherwise, return NULL_RTX. This optimization can be performed when { xreg1, xval1 } and { xreg2, xval2 } are equal as sets. It can be done in such a way that no difficult branches occur. */ @@ -4063,7 +4063,7 @@ avr_optimize_casesi (rtx_insn *insns[5], rtx *xop) // SIGN_EXTEND or ZERO_EXTEND. rtx_code code = GET_CODE (xop[10]); - // Lower index, upper index (plus one) and range of case calues. + // Lower index, upper index (plus one) and range of case values. HOST_WIDE_INT low_idx = -INTVAL (xop[1]); HOST_WIDE_INT num_idx = INTVAL (xop[2]); HOST_WIDE_INT hig_idx = low_idx + num_idx; @@ -4358,7 +4358,7 @@ struct AVR_LdSt_Props { bool has_postinc, has_predec, has_ldd; // The insn printers will use POST_INC or PRE_DEC addressing, no matter - // what adressing modes we are feeding into them. + // what addressing modes we are feeding into them. bool want_postinc, want_predec; AVR_LdSt_Props (int regno, bool store_p, bool volatile_p, addr_space_t as) @@ -5038,7 +5038,7 @@ avr_pass_split_nzb::split_nzb_insns () ////////////////////////////////////////////////////////////////////////////// -// Split shift insns after peephole2 / befor avr-fuse-move. +// Split shift insns after peephole2 / before avr-fuse-move. static const pass_data avr_pass_data_split_after_peephole2 = { @@ -5889,7 +5889,7 @@ make_avr_pass_fuse_move (gcc::context *ctxt) return new avr_pass_fuse_move (ctxt, "avr-fuse-move"); } -// Split insns after peephole2 / befor avr-fuse-move. +// Split insns after peephole2 / before avr-fuse-move. rtl_opt_pass * make_avr_pass_split_after_peephole2 (gcc::context *ctxt) diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index 2f0ed2e491ab..40dbe168af4c 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -596,7 +596,7 @@ avr_option_override (void) if (!avr_set_core_architecture ()) return; - /* Sould be set by avr-common.cc */ + /* Should be set by avr-common.cc */ gcc_assert (avropt_long_double >= avropt_double && avropt_double >= 32); /* RAM addresses of some SFRs common to all devices in respective arch. */ @@ -981,7 +981,7 @@ avr_can_inline_p (tree /* caller */, tree /* callee */) /* Implement `TARGET_SET_CURRENT_FUNCTION'. */ -/* Sanity cheching for above function attributes. */ +/* Sanity checking for above function attributes. */ static void avr_set_current_function (tree decl) @@ -2172,7 +2172,7 @@ avr_expand_epilogue (bool sibcall_p) if (isr_p) { /* Restore RAMPZ/Y/X/D using tmp_reg as scratch. - The conditions to restore them must be tha same as in prologue. */ + The conditions to restore them must be the same as in prologue. */ if (AVR_HAVE_RAMPZ && TEST_HARD_REG_BIT (set, REG_Z) @@ -3110,7 +3110,7 @@ avr_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, if (!libname && stdarg_p (fntype)) cum->nregs = 0; - /* Assume the calle may be tail called */ + /* Assume the callee may be tail called */ cfun->machine->sibcall_fails = false; } @@ -3495,7 +3495,7 @@ reg_unused_after (rtx_insn *insn, rtx reg) /* Return true when REGNO is set by INSN but not used by the following code. The difference to reg_unused_after() is that reg_unused_after() returns - true for the entire result even when the result *IS* being used atfer. */ + true for the entire result even when the result *IS* being used after. */ static bool avr_result_regno_unused_p (rtx_insn *insn, unsigned regno) @@ -3695,7 +3695,7 @@ avr_out_lpm_no_lpmx (rtx_insn *insn, rtx *xop, int *plen) } -/* If PLEN == NULL: Ouput instructions to load a value from a memory location +/* If PLEN == NULL: Output instructions to load a value from a memory location OP[1] in AS1 to register OP[0]. If PLEN != 0 set *PLEN to the length in words of the instruction sequence. Return "". */ @@ -6584,7 +6584,7 @@ avr_out_compare (rtx_insn *insn, rtx *xop, int *plen) const rtx_code cond = compare_condition (insn); const bool eqne_p = cond == EQ || cond == NE; - /* Comparisons == +/-1 and != +/-1 can be done similar to camparing + /* Comparisons == +/-1 and != +/-1 can be done similar to comparing against 0 by ORing the bytes. This is one instruction shorter. Notice that 64-bit comparisons are always against reg:ALL8 18 (ACC_A) and therefore don't use this. */ @@ -8670,7 +8670,7 @@ avr_out_plus_ext (rtx_insn *insn, rtx *yop, int *plen) ? "sbci %0,0" CR_TAB "sbrc %1,7" CR_TAB "inc %0" : "sbc %0,__zero_reg__" CR_TAB "sbrc %1,7" CR_TAB "inc %0"; - // A register that containts 8 copies of $1.msb. + // A register that contains 8 copies of $1.msb. rtx ext_reg = ext == ZERO_EXTEND ? zero_reg_rtx : NULL_RTX; if (plen) @@ -10691,7 +10691,7 @@ avr_out_fract (rtx_insn *insn, rtx operands[], bool intsigned, int *plen) { /* We are going to override the MSB. If we shift right, store the MSB in the Carry flag. This is only needed if - we don't sign-extend becaue with sign-extension the MSB + we don't sign-extend because with sign-extension the MSB (the sign) will be produced by the sign extension. */ avr_asm_len ("lsr %0", &all_regs_rtx[src_msb], plen, 1); @@ -15601,7 +15601,7 @@ avr_nonzero_bits_lsr_operands_p (rtx_code code, rtx *op) XOP[2] # Bytes to copy Return TRUE if the expansion is accomplished. - Return FALSE if the operand compination is not supported. */ + Return FALSE if the operand combination is not supported. */ bool avr_emit_cpymemhi (rtx *xop) diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h index 95ab03cb8e70..3c0b1b4283b2 100644 --- a/gcc/config/avr/avr.h +++ b/gcc/config/avr/avr.h @@ -499,7 +499,7 @@ extern const char *avr_no_devlib (int, const char**); { "no-devlib", avr_no_devlib }, \ { "device-specs-file", avr_devicespecs_file }, -/* Driver self specs has lmited functionality w.r.t. '%s' for dynamic specs. +/* Driver self specs has limited functionality w.r.t. '%s' for dynamic specs. Apply '%s' to a static string to inflate the file (directory) name which is used to diagnose problems with reading the specs file. */ @@ -586,7 +586,7 @@ struct GTY(()) machine_function bool yes; /* 'true' if this function is allowed to use "*gasisr" insns. */ bool maybe; - /* The register numer as printed by the Done chunk. */ + /* The register number as printed by the Done chunk. */ int regno; } gasisr; diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 6a36c8ae30ed..3b70dc18aab3 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -193,8 +193,8 @@ ;; The following ISA attributes are actually not architecture specific, ;; but depend on (optimization) options. This is because the "enabled" -;; attribut can't depend on more than one other attribute. This means -;; that 3op must work for all ISAs, and hence a 'flat' attribue scheme +;; attribute can't depend on more than one other attribute. This means +;; that 3op must work for all ISAs, and hence a 'flat' attribute scheme ;; can be used (as opposed to a true cartesian product). ;; 3op : alternative is a 3-operand insn @@ -397,7 +397,7 @@ ;; The following is used by nonlocal_goto and setjmp. ;; The receiver pattern will create no instructions since internally ;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28 -;; This avoids creating add/sub offsets in frame_pointer save/resore. +;; This avoids creating add/sub offsets in frame_pointer save/restore. ;; The 'null' receiver also avoids problems with optimisation ;; not recognising incoming jmp and removing code that resets frame_pointer. ;; The code derived from builtins.cc. @@ -6775,7 +6775,7 @@ ;; without a comparison does not require a scratch. With the peep2 approach ;; below, we can get a scratch from the peep2 framework without increasing ;; the register pressure, whereas cmpelim doesn't offer such a feature. -;; When no scratch is available, then we just don't perform the optimizaton, +;; When no scratch is available, then we just don't perform the optimization, ;; i.e. the comparison against 0 won't be optimized away, which is preferred ;; over increasing the register pressure -- in many cases without reason -- ;; which might result in additional spills. @@ -8090,7 +8090,7 @@ ;; AND Rm, Rn ;; BRNE .La ;; -;; shall not be superseeded. With a respective combine pattern +;; shall not be superseded. With a respective combine pattern ;; the latter sequence would be ;; ;; AND Rm, Rn @@ -8633,7 +8633,7 @@ DONE; }) -;; Actually, it's too late now to work out address spaces known at compiletime. +;; Actually, it's too late now to work out address spaces known at compile time. ;; Best place would be to fold ADDR_SPACE_CONVERT_EXPR in avr_fold_builtin. ;; However, avr_addr_space_convert can add some built-in knowledge for PSTR ;; so that ADDR_SPACE_CONVERT_EXPR in the built-in must not be resolved. diff --git a/gcc/config/avr/builtins.def b/gcc/config/avr/builtins.def index 5820939393d4..e52172d51109 100644 --- a/gcc/config/avr/builtins.def +++ b/gcc/config/avr/builtins.def @@ -18,7 +18,7 @@ /* This file contains the definitions and documentation for the builtins defined in the AVR part of the GNU compiler. - Befor including this file, define a macro + Before including this file, define a macro DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, LIBNAME, ATTRS) @@ -65,7 +65,7 @@ DEF_BUILTIN (INSERT_BITS, 3, uintQI_ftype_uintSI_uintQI_uintQI, insert_bits, NUL DEF_BUILTIN (FLASH_SEGMENT, 1, intQI_ftype_const_memx_ptr, flash_segment, NULL, attr_const) -/* strlen for ASes so that __builtin_constant_p can be used wthout raising +/* strlen for ASes so that __builtin_constant_p can be used without raising a diagnostic from -Waddr-space-convert in some AVR-LibC headers. */ DEF_BUILTIN (STRLEN_FLASH, 1, strlen_flash_node, nothing, "__strlen_P", attr_const) // AVR-LibC DEF_BUILTIN (STRLEN_FLASHX, 1, strlen_flashx_node, nothing, "strlen_PF", attr_const) // AVR-LibC diff --git a/gcc/config/avr/specs.h b/gcc/config/avr/specs.h index 1fca4a1d6eec..b50f7040941e 100644 --- a/gcc/config/avr/specs.h +++ b/gcc/config/avr/specs.h @@ -20,7 +20,7 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ -/* Default specs layout. The actual definitions might be superseeded +/* Default specs layout. The actual definitions might be superseded by device- or OS- specific files, like avrlibc.h, ../rtems.h, etc. The specs are repeated in the device specs files. Subspecs are specs known to GCC or specs defined in the device specs files. */ diff --git a/libgcc/config/avr/libf7/libf7.c b/libgcc/config/avr/libf7/libf7.c index d258f2b5ab25..ec4f202455f0 100644 --- a/libgcc/config/avr/libf7/libf7.c +++ b/libgcc/config/avr/libf7/libf7.c @@ -959,7 +959,7 @@ void f7_addsub (f7_t *cc, const f7_t *aa, const f7_t *bb, bool neg_b) // From this point on, no more access aa->flags or bb->flags // to avoid early-clobber when writing cc->flags. - // Hande NaNs. + // Handle NaNs. if (f7_class_nan (a_class | b_class)) return f7_set_nan (cc); @@ -1035,7 +1035,7 @@ void f7_madd_msub (f7_t *cc, const f7_t *aa, const f7_t *bb, const f7_t *dd, uint8_t x_sign = f7_signbit (xx); int16_t x_expo = xx->expo; f7_addsub (xx, xx, dd, neg_d); - // Now add LSB. If cancellation occured in the add / sub, then we have the + // Now add LSB. If cancellation occurred in the add / sub, then we have the // chance of extra 8 bits of precision. Turn LSByte into f7_t. f7_clr (cc); cc->expo = sub_ssat16 (x_expo, F7_MANT_BITS); diff --git a/libgcc/config/avr/libf7/libf7.h b/libgcc/config/avr/libf7/libf7.h index 825cb68142b9..545679145574 100644 --- a/libgcc/config/avr/libf7/libf7.h +++ b/libgcc/config/avr/libf7/libf7.h @@ -670,7 +670,7 @@ extern void f7_Isqrt (f7_t*); extern void f7_Isquare (f7_t*); extern f7_t* f7_Ildexp (f7_t*, int); -// Protoypes for some functions from libf7-asm.sx. +// Prototypes for some functions from libf7-asm.sx. F7_CONST extern uint16_t f7_sqrt16_round (uint16_t) F7ASM(f7_sqrt16_round_asm); F7_CONST extern uint8_t f7_sqrt16_floor (uint16_t) F7ASM(f7_sqrt16_floor_asm); extern void f7_addsub_mant_scaled_asm (f7_t*, const f7_t*, const f7_t*, uint8_t);
