https://gcc.gnu.org/g:72102504e3e5c3bce6eb630c13d653f82394e53d
commit r17-1116-g72102504e3e5c3bce6eb630c13d653f82394e53d Author: Dhruv Chawla <[email protected]> Date: Wed May 20 11:49:03 2026 +0000 nds32: Fix typos in various files Signed-off-by: Dhruv Chawla <[email protected]> gcc/ChangeLog: * common/config/nds32/nds32-common.cc (nds32_except_unwind_info): Fix typos. * config/nds32/constants.md: Likewise. * config/nds32/constraints.md: Likewise. * config/nds32/nds32-cost.cc (nds32_rtx_costs_speed_prefer): Likewise. * config/nds32/nds32-dspext.md: Likewise. * config/nds32/nds32-e8.md: Likewise. * config/nds32/nds32-fp-as-gp.cc (nds32_fp_as_gp_check_available): Likewise. * config/nds32/nds32-intrinsic.cc (nds32_expand_priority_builtin): Likewise. * config/nds32/nds32-isr.cc (nds32_emit_isr_vector_section): Likewise. (nds32_asm_file_end_for_isr): Likewise. * config/nds32/nds32-md-auxiliary.cc (output_cond_branch): Likewise. (nds32_expand_cbranch): Likewise. (nds32_expand_float_cstore): Likewise. (nds32_expand_movcc): Likewise. (nds32_output_stack_pop): Likewise. (nds32_output_return): Likewise. (nds32_split_sms): Likewise. (nds32_legitimize_tls_address): Likewise. * config/nds32/nds32-memory-manipulation.cc (nds32_expand_cpymemsi_unroll): Likewise. (nds32_expand_load_multiple): Likewise. * config/nds32/nds32-multiple.md: Likewise. * config/nds32/nds32-n7.md: Likewise. * config/nds32/nds32-n8.md: Likewise. * config/nds32/nds32-n9-2r1w.md: Likewise. * config/nds32/nds32-pipelines-auxiliary.cc (extract_nth_access_reg): Likewise. (pbsada_insn_ra_rb_dep_reg_p): Likewise. * config/nds32/nds32-predicates.cc (nds32_can_use_bset_p): Likewise. (nds32_can_use_btgl_p): Likewise. (nds32_symbol_load_store_p): Likewise. * config/nds32/nds32-protos.h (nds32_cond_move_p): Likewise. (nds32_mem_format): Likewise. * config/nds32/nds32-relax-opt.cc (nds32_plus_reg_load_store_p): Likewise. * config/nds32/nds32-utils.cc (extract_offset_rtx): Likewise. * config/nds32/nds32.cc (nds32_compute_stack_frame): Likewise. (nds32_emit_stack_pop_multiple): Likewise. (nds32_emit_stack_v3pop): Likewise. (nds32_can_change_mode_class): Likewise. (nds32_arg_partial_bytes): Likewise. (nds32_function_ok_for_sibcall): Likewise. (nds32_register_move_cost): Likewise. (nds32_print_operand): Likewise. (nds32_merge_decl_attributes): Likewise. (nds32_insert_attributes): Likewise. (nds32_init_libfuncs): Likewise. (nds32_expand_epilogue_v3pop): Likewise. (nds32_can_use_return_insn): Likewise. (nds32_target_alignment): Likewise. (nds32_split_double_word_load_store_p): Likewise. * config/nds32/nds32.h (enum nds32_builtins): Likewise. (CASE_VECTOR_MODE): Likewise. * config/nds32/nds32.md: Likewise. * config/nds32/nds32_intrinsic.h (__attribute__): Likewise. * config/nds32/nds32_isr.h: Likewise. libgcc/ChangeLog: * config/nds32/initfini.c: Fix typos. * config/nds32/linux-atomic.c: Likewise. Diff: --- gcc/common/config/nds32/nds32-common.cc | 8 ++--- gcc/config/nds32/constants.md | 2 +- gcc/config/nds32/constraints.md | 2 +- gcc/config/nds32/nds32-cost.cc | 2 +- gcc/config/nds32/nds32-dspext.md | 6 ++-- gcc/config/nds32/nds32-e8.md | 2 +- gcc/config/nds32/nds32-fp-as-gp.cc | 2 +- gcc/config/nds32/nds32-intrinsic.cc | 2 +- gcc/config/nds32/nds32-isr.cc | 4 +-- gcc/config/nds32/nds32-md-auxiliary.cc | 22 ++++++------- gcc/config/nds32/nds32-memory-manipulation.cc | 4 +-- gcc/config/nds32/nds32-multiple.md | 4 +-- gcc/config/nds32/nds32-n7.md | 6 ++-- gcc/config/nds32/nds32-n8.md | 6 ++-- gcc/config/nds32/nds32-n9-2r1w.md | 4 +-- gcc/config/nds32/nds32-pipelines-auxiliary.cc | 4 +-- gcc/config/nds32/nds32-predicates.cc | 6 ++-- gcc/config/nds32/nds32-protos.h | 4 +-- gcc/config/nds32/nds32-relax-opt.cc | 2 +- gcc/config/nds32/nds32-utils.cc | 2 +- gcc/config/nds32/nds32.cc | 46 +++++++++++++-------------- gcc/config/nds32/nds32.h | 4 +-- gcc/config/nds32/nds32.md | 6 ++-- gcc/config/nds32/nds32_intrinsic.h | 2 +- gcc/config/nds32/nds32_isr.h | 2 +- libgcc/config/nds32/initfini.c | 2 +- libgcc/config/nds32/linux-atomic.c | 2 +- 27 files changed, 79 insertions(+), 79 deletions(-) diff --git a/gcc/common/config/nds32/nds32-common.cc b/gcc/common/config/nds32/nds32-common.cc index 2bc565f11bd9..03cce2b38b10 100644 --- a/gcc/common/config/nds32/nds32-common.cc +++ b/gcc/common/config/nds32/nds32-common.cc @@ -94,7 +94,7 @@ static const struct default_options nds32_option_optimization_table[] = { OPT_LEVELS_ALL, OPT_fomit_frame_pointer, NULL, 1 }, /* Enable -mrelax-hint by default at all optimization levels. */ { OPT_LEVELS_ALL, OPT_mrelax_hint, NULL, 1 }, - /* Enalbe -malways-align by default at -O1 and above, but not -Os or -Og. */ + /* Enable -malways-align by default at -O1 and above, but not -Os or -Og. */ { OPT_LEVELS_1_PLUS_SPEED_ONLY, OPT_malways_align, NULL, 1 }, /* Enable -mv3push by default at -Os, but it is useless under V2 ISA. */ { OPT_LEVELS_SIZE, OPT_mv3push, NULL, 1 }, @@ -129,9 +129,9 @@ nds32_except_unwind_info (struct gcc_options *opts ATTRIBUTE_UNUSED) Other MASK_XXX flags are set individually. By default we enable TARGET_16_BIT : Generate 16/32 bit mixed length instruction. - TARGET_EXT_PERF : Generate performance extention instrcution. - TARGET_EXT_PERF2 : Generate performance extention version 2 instrcution. - TARGET_EXT_STRING : Generate string extention instrcution. + TARGET_EXT_PERF : Generate performance extension instruction. + TARGET_EXT_PERF2 : Generate performance extension version 2 instruction. + TARGET_EXT_STRING : Generate string extension instruction. TARGET_HW_ABS : Generate hardware abs instruction. TARGET_CMOV : Generate conditional move instruction. */ #undef TARGET_DEFAULT_TARGET_FLAGS diff --git a/gcc/config/nds32/constants.md b/gcc/config/nds32/constants.md index 33c4f7670707..455db605de56 100644 --- a/gcc/config/nds32/constants.md +++ b/gcc/config/nds32/constants.md @@ -1,4 +1,4 @@ -;; Constant defintions of Andes NDS32 cpu for GNU compiler +;; Constant definitions of Andes NDS32 cpu for GNU compiler ;; Copyright (C) 2012-2026 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; diff --git a/gcc/config/nds32/constraints.md b/gcc/config/nds32/constraints.md index 2933ceb501a1..10f0e9f0f264 100644 --- a/gcc/config/nds32/constraints.md +++ b/gcc/config/nds32/constraints.md @@ -20,7 +20,7 @@ ;; Check 16.8.7 Defining Machine-Specific Constraints for detail. -;; NO contrains can be prefixed with: E F V X g i m n o p r s +;; NO constraints can be prefixed with: E F V X g i m n o p r s ;; Machine-dependent integer: I J K L M N O P ;; Machine-dependent floating: G H diff --git a/gcc/config/nds32/nds32-cost.cc b/gcc/config/nds32/nds32-cost.cc index 434ab40f0ce8..c8473e4257a4 100644 --- a/gcc/config/nds32/nds32-cost.cc +++ b/gcc/config/nds32/nds32-cost.cc @@ -215,7 +215,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED, if (NDS32_EXT_DSP_P ()) { /* We prefer (and (ior) (ior)) than (ior (and) (and)) for - synthetize pk** and insb instruction. */ + synthesize pk** and insb instruction. */ if (code == AND && GET_CODE (op0) == IOR && GET_CODE (op1) == IOR) return COSTS_N_INSNS (1); diff --git a/gcc/config/nds32/nds32-dspext.md b/gcc/config/nds32/nds32-dspext.md index 9bdf3ead42a2..72630b12f064 100644 --- a/gcc/config/nds32/nds32-dspext.md +++ b/gcc/config/nds32/nds32-dspext.md @@ -1447,7 +1447,7 @@ [(set_attr "type" "dinsb") (set_attr "length" "4")]) -;; Intermedium pattern for synthetize insvsiqi_internal +;; Intermedium pattern for synthesize insvsiqi_internal ;; v0 = ((v1 & 0xff) << 8) (define_insn_and_split "and0xff_s8" [(set (match_operand:SI 0 "register_operand" "=r") @@ -4342,7 +4342,7 @@ [(set_attr "type" "dmac") (set_attr "length" "4")]) -;; mada for synthetize smalda +;; mada for synthesize smalda (define_insn_and_split "mada1" [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI @@ -4407,7 +4407,7 @@ DONE; }) -;; sms for synthetize smalds +;; sms for synthesize smalds (define_insn_and_split "sms1" [(set (match_operand:SI 0 "register_operand" "= r") (minus:SI diff --git a/gcc/config/nds32/nds32-e8.md b/gcc/config/nds32/nds32-e8.md index 906936a68c8d..079b10f83fa3 100644 --- a/gcc/config/nds32/nds32-e8.md +++ b/gcc/config/nds32/nds32-e8.md @@ -31,7 +31,7 @@ ;; IF - Instruction Fetch ;; II - Instruction Issue / Address Generation ;; EX - Instruction Execution -;; EXD - Psuedo Stage / Load Data Completion +;; EXD - Pseudo Stage / Load Data Completion (define_cpu_unit "e8_ii" "nds32_e8_machine") (define_cpu_unit "e8_ex" "nds32_e8_machine") diff --git a/gcc/config/nds32/nds32-fp-as-gp.cc b/gcc/config/nds32/nds32-fp-as-gp.cc index 550d6ef4f391..f9dde4bf02bb 100644 --- a/gcc/config/nds32/nds32-fp-as-gp.cc +++ b/gcc/config/nds32/nds32-fp-as-gp.cc @@ -116,7 +116,7 @@ nds32_fp_as_gp_check_available (void) 3. Not optimize for size. 4. Need frame pointer. 5. If $fp is already required to be saved, - it means $fp is already choosen by register allocator. + it means $fp is already chosen by register allocator. Thus we better not to use it for fp_as_gp optimization. 6. This function is a vararg function. DO NOT apply fp_as_gp optimization on this function diff --git a/gcc/config/nds32/nds32-intrinsic.cc b/gcc/config/nds32/nds32-intrinsic.cc index b0705778beda..0a57d039380f 100644 --- a/gcc/config/nds32/nds32-intrinsic.cc +++ b/gcc/config/nds32/nds32-intrinsic.cc @@ -477,7 +477,7 @@ nds32_expand_priority_builtin (enum insn_code icode, tree exp, rtx target, rtx op1 = nds32_read_argument (exp, 1); /* set_int_priority intrinsic function that two arguments are immediate, - so check whether auguments are immedite. */ + so check whether arguments are immediate. */ if (!nds32_check_constant_argument (icode, 0, op0, name)) return NULL_RTX; diff --git a/gcc/config/nds32/nds32-isr.cc b/gcc/config/nds32/nds32-isr.cc index 14c005eb3154..8341113a15d6 100644 --- a/gcc/config/nds32/nds32-isr.cc +++ b/gcc/config/nds32/nds32-isr.cc @@ -464,7 +464,7 @@ nds32_emit_isr_vector_section (int vector_id) For pushing GPRs, there are four variations for 16-byte vector content and we have to handle each combination. For preparing software vid, note that the vid need to - be substracted vector_number_offset. */ + be subtracted vector_number_offset. */ if (TARGET_REDUCED_REGS) { if (nds32_isr_vectors[vector_id].save_reg == NDS32_SAVE_ALL) @@ -899,7 +899,7 @@ void nds32_asm_file_end_for_isr (void) if (nds32_isr_vectors[i].category == NDS32_ISR_INTERRUPT || nds32_isr_vectors[i].category == NDS32_ISR_EXCEPTION) { - /* Found one vector which is interupt or exception. + /* Found one vector which is interrupt or exception. Output its jmptbl and vector section content. */ fprintf (asm_out_file, "\t! interrupt/exception vector %02d\n", i); fprintf (asm_out_file, "\t! security level: %d\n", diff --git a/gcc/config/nds32/nds32-md-auxiliary.cc b/gcc/config/nds32/nds32-md-auxiliary.cc index 19f1424f63b2..f45f63daa7d3 100644 --- a/gcc/config/nds32/nds32-md-auxiliary.cc +++ b/gcc/config/nds32/nds32-md-auxiliary.cc @@ -138,7 +138,7 @@ output_cond_branch (int code, const char *suffix, bool r5_p, { /* This is special case for beqs38 and bnes38, second operand 2 can't be $r5 and it's almost meanless, - however it may occur after copy propgation. */ + however it may occur after copy propagation. */ if (code == EQ) { /* $r5 == $r5 always taken! */ @@ -416,9 +416,9 @@ nds32_expand_cbranch (rtx *operands) /* We want to plus 1 into the integer value of operands[2] to create 'slt' instruction. - This caculation is performed on the host machine, + This calculation is performed on the host machine, which may be 64-bit integer. - So the meaning of caculation result may be + So the meaning of calculation result may be different from the 32-bit nds32 target. For example: @@ -955,11 +955,11 @@ nds32_expand_float_cstore (rtx *operands) reg_R = (reg_A <= reg_B) --> fcmple reg_R, reg_A, reg_B reg_R = (reg_A == reg_B) --> fcmpeq reg_R, reg_A, reg_B - ORDERED: reverse condition and using xor insturction to achieve 'ORDERED'. + ORDERED: reverse condition and using xor instruction to achieve 'ORDERED'. reg_R = (reg_A != reg_B) --> fcmpun reg_R, reg_A, reg_B xor reg_R, reg_R, const1_rtx - NE: reverse condition and using xor insturction to achieve 'NE'. + NE: reverse condition and using xor instruction to achieve 'NE'. reg_R = (reg_A != reg_B) --> fcmpeq reg_R, reg_A, reg_B xor reg_R, reg_R, const1_rtx */ switch (code) @@ -1088,7 +1088,7 @@ nds32_expand_movcc (rtx *operands) else { /* This emit_insn will create corresponding 'slt/slts' - insturction. */ + instruction. */ if (new_code == LT) emit_insn (gen_slts_compare (tmp, cmp_op0, cmp_op1)); else if (new_code == LTU) @@ -2169,7 +2169,7 @@ nds32_output_stack_pop (rtx par_rtx ATTRIBUTE_UNUSED) We have to consider alloca issue as well. If the function does call alloca(), the stack pointer is not fixed. In that case, we cannot use 'pop25 Re,imm8u' directly. - We have to caculate stack pointer from frame pointer + We have to calculate stack pointer from frame pointer and then use 'pop25 Re,0'. */ sp_adjust = cfun->machine->local_size + cfun->machine->out_args_size @@ -2184,7 +2184,7 @@ nds32_output_stack_pop (rtx par_rtx ATTRIBUTE_UNUSED) if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) { /* If has fpr need to restore, the $sp on callee saved fpr - position, so we need to consider gpr pading bytes and + position, so we need to consider gpr padding bytes and callee saved fpr size. */ sp_adjust = cfun->machine->callee_saved_area_gpr_padding_bytes + cfun->machine->callee_saved_fpr_regs_size; @@ -2269,7 +2269,7 @@ nds32_output_return (void) We have to consider alloca issue as well. If the function does call alloca(), the stack pointer is not fixed. In that case, we cannot use 'pop25 Re,imm8u' directly. - We have to caculate stack pointer from frame pointer + We have to calculate stack pointer from frame pointer and then use 'pop25 Re,0'. */ sp_adjust = cfun->machine->local_size + cfun->machine->out_args_size @@ -3132,7 +3132,7 @@ nds32_split_sms (rtx out, rtx in0, rtx in1, emit_insn (gen_subsi3 (out, result0, result1)); } -/* Spilt a doubleword instrucion to two single word instructions. */ +/* Spilt a doubleword instruction to two single word instructions. */ void nds32_spilt_doubleword (rtx *operands, bool load_p) { @@ -3689,7 +3689,7 @@ nds32_legitimize_tls_address (rtx x) pat = gen_rtx_CONST (SImode, pat); reg0 = gen_rtx_REG (Pmode, 0); - /* If we can confirm all clobber reigsters, it doesn't have to use call + /* If we can confirm all clobber registers, it doesn't have to use call instruction. */ insns = emit_call_insn (gen_tls_desc (pat, GEN_INT (relax_group_id))); use_reg (&CALL_INSN_FUNCTION_USAGE (insns), pic_offset_table_rtx); diff --git a/gcc/config/nds32/nds32-memory-manipulation.cc b/gcc/config/nds32/nds32-memory-manipulation.cc index b15b50078b28..bc9644cd4b6b 100644 --- a/gcc/config/nds32/nds32-memory-manipulation.cc +++ b/gcc/config/nds32/nds32-memory-manipulation.cc @@ -404,7 +404,7 @@ nds32_expand_cpymemsi_unroll (rtx dstmem, rtx srcmem, bool align_to_4_bytes = (INTVAL (alignment) & 3) == 0; bool align_to_2_bytes = (INTVAL (alignment) & 1) == 0; - /* Because reduced-set regsiters has few registers + /* Because reduced-set registers has few registers (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31' cannot be used for register allocation), using 8 registers (32 bytes) for moving memory block @@ -1080,7 +1080,7 @@ nds32_expand_load_multiple (int base_regno, int count, rtx new_addr, mem, reg; /* Generate a unaligned load to prevent load instruction pull out from - parallel, and then it will generate lwi, and lose unaligned acces */ + parallel, and then it will generate lwi, and lose unaligned access */ if (count == 1) { reg = gen_rtx_REG (SImode, base_regno); diff --git a/gcc/config/nds32/nds32-multiple.md b/gcc/config/nds32/nds32-multiple.md index 7c7bee2fde28..2015aa107075 100644 --- a/gcc/config/nds32/nds32-multiple.md +++ b/gcc/config/nds32/nds32-multiple.md @@ -33,7 +33,7 @@ { int maximum; - /* Because reduced-set regsiters has few registers + /* Because reduced-set registers has few registers (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31' cannot be used for register allocation), using 8 registers for load_multiple may easily consume all of them. @@ -1882,7 +1882,7 @@ { int maximum; - /* Because reduced-set regsiters has few registers + /* Because reduced-set registers has few registers (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31' cannot be used for register allocation), using 8 registers for store_multiple may easily consume all of them. diff --git a/gcc/config/nds32/nds32-n7.md b/gcc/config/nds32/nds32-n7.md index 5957145e3ff9..d6ca59506fc5 100644 --- a/gcc/config/nds32/nds32-n7.md +++ b/gcc/config/nds32/nds32-n7.md @@ -36,7 +36,7 @@ ;; Register File Access ;; Instruction Execution ;; Interrupt Handling -;; EXD - Psuedo Stage +;; EXD - Pseudo Stage ;; Load Data Completion (define_cpu_unit "n7_ii" "nds32_n7_machine") @@ -229,7 +229,7 @@ ;; Require operands at II. ;; MOVD44_E ;; A double-word move instruction needs two micro-operations because the -;; reigster ports is 2R1W. The first micro-operation writes an even number +;; register ports is 2R1W. The first micro-operation writes an even number ;; register, and the second micro-operation writes an odd number register. ;; Each input operand is required at II for each micro-operation. The letter ;; 'E' stands for even. @@ -239,7 +239,7 @@ ;; and Rb at II. The second micro-options does the accumulation, which ;; requires the operand Rt at II. ;; ADDR_IN_MOP(N) -;; Because the reigster port is 2R1W, some load/store instructions are +;; Because the register port is 2R1W, some load/store instructions are ;; separated into many micro-operations. N denotes the address input is ;; required by the N-th micro-operation. Such operand is required at II. ;; ST_bi diff --git a/gcc/config/nds32/nds32-n8.md b/gcc/config/nds32/nds32-n8.md index 3b6368fcd514..43c328dc3f1e 100644 --- a/gcc/config/nds32/nds32-n8.md +++ b/gcc/config/nds32/nds32-n8.md @@ -31,7 +31,7 @@ ;; IF - Instruction Fetch ;; II - Instruction Issue / Address Generation ;; EX - Instruction Execution -;; EXD - Psuedo Stage / Load Data Completion +;; EXD - Pseudo Stage / Load Data Completion (define_cpu_unit "n8_ii" "nds32_n8_machine") (define_cpu_unit "n8_ex" "nds32_n8_machine") @@ -233,7 +233,7 @@ ;; MOVD44_O ;; A double-word move instruction needs to write registers twice. Because ;; the register port is 2R1W, two micro-operations are required. The even -;; number reigster is updated by the first one, and the odd number register +;; number register is updated by the first one, and the odd number register ;; is updated by the second one. Each of the results is ready at EX. ;; The letter 'O' stands for odd. ;; DIV_Rs @@ -254,7 +254,7 @@ ;; and Rb at EX. The second micro-options does the accumulation, which ;; requires the operand Rt at EX. ;; ADDR_IN_MOP(N) -;; Because the reigster port is 2R1W, some load/store instructions are +;; Because the register port is 2R1W, some load/store instructions are ;; separated into many micro-operations. N denotes the address input is ;; required by the N-th micro-operation. Such operand is required at II. ;; ST_bi diff --git a/gcc/config/nds32/nds32-n9-2r1w.md b/gcc/config/nds32/nds32-n9-2r1w.md index aff9fef40a0c..4e73a09de77e 100644 --- a/gcc/config/nds32/nds32-n9-2r1w.md +++ b/gcc/config/nds32/nds32-n9-2r1w.md @@ -271,7 +271,7 @@ ;; There are N micro-operations within an instruction that loads multiple ;; words. The result produced by the M-th micro-operation is sent to ;; consumers. The result is ready at MM. If the base register should be -;; updated, an extra micro-operation is apppended to the end of the +;; updated, an extra micro-operation is appended to the end of the ;; sequence, and the result is ready at EX. ;; MUL, MAC ;; Compute data in the multiply-adder and produce the data. The result @@ -289,7 +289,7 @@ ;; micro-operation, and there are some latencies if data dependency occurs. ;; MOVD44_E ;; A double-word move instruction needs two micro-operations because the -;; reigster ports is 2R1W. The first micro-operation writes an even number +;; register ports is 2R1W. The first micro-operation writes an even number ;; register, and the second micro-operation writes an odd number register. ;; Each input operand is required at EX for each micro-operation. MOVD44_E ;; stands for the first micro-operation. diff --git a/gcc/config/nds32/nds32-pipelines-auxiliary.cc b/gcc/config/nds32/nds32-pipelines-auxiliary.cc index b73bc08b8323..13be995b3c63 100644 --- a/gcc/config/nds32/nds32-pipelines-auxiliary.cc +++ b/gcc/config/nds32/nds32-pipelines-auxiliary.cc @@ -288,7 +288,7 @@ extract_nth_access_reg (rtx_insn *insn, int index) } } -/* Determine if the latency is occured when the consumer PBSADA_INSN uses the +/* Determine if the latency is occurred when the consumer PBSADA_INSN uses the value of DEF_REG in its Ra or Rb fields. */ bool pbsada_insn_ra_rb_dep_reg_p (rtx pbsada_insn, rtx def_reg) @@ -306,7 +306,7 @@ pbsada_insn_ra_rb_dep_reg_p (rtx pbsada_insn, rtx def_reg) return false; } -/* Determine if the latency is occured when the consumer PBSADA_INSN uses the +/* Determine if the latency is occurred when the consumer PBSADA_INSN uses the value of DEF_REG in its Rt field. */ bool pbsada_insn_rt_dep_reg_p (rtx pbsada_insn, rtx def_reg) diff --git a/gcc/config/nds32/nds32-predicates.cc b/gcc/config/nds32/nds32-predicates.cc index a1f1941f4230..3d4a0ecc17ce 100644 --- a/gcc/config/nds32/nds32-predicates.cc +++ b/gcc/config/nds32/nds32-predicates.cc @@ -379,7 +379,7 @@ nds32_can_use_bset_p (HOST_WIDE_INT ival) int one_bit_count; unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode); - /* Caculate the number of 1-bit of ival, if there is only one 1-bit, + /* Calculate the number of 1-bit of ival, if there is only one 1-bit, it is ok to perform 'bset' operation. */ one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival) & mask); @@ -395,7 +395,7 @@ nds32_can_use_btgl_p (HOST_WIDE_INT ival) int one_bit_count; unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode); - /* Caculate the number of 1-bit of ival, if there is only one 1-bit, + /* Calculate the number of 1-bit of ival, if there is only one 1-bit, it is ok to perform 'btgl' operation. */ one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival) & mask); @@ -452,7 +452,7 @@ nds32_symbol_load_store_p (rtx_insn *insn) return false; } -/* Vaild memory operand for floating-point loads and stores */ +/* Valid memory operand for floating-point loads and stores */ bool nds32_float_mem_operand_p (rtx op) { diff --git a/gcc/config/nds32/nds32-protos.h b/gcc/config/nds32/nds32-protos.h index 2e939301339a..42d15d9d7839 100644 --- a/gcc/config/nds32/nds32-protos.h +++ b/gcc/config/nds32/nds32-protos.h @@ -223,11 +223,11 @@ extern bool symbolic_reference_mentioned_p (rtx); extern int nds32_cond_move_p (rtx); -/* Auxiliary functions to identify 16 bit addresing mode. */ +/* Auxiliary functions to identify 16 bit addressing mode. */ extern enum nds32_16bit_address_type nds32_mem_format (rtx); -/* Auxiliary functions to identify floating-point addresing mode. */ +/* Auxiliary functions to identify floating-point addressing mode. */ extern bool nds32_float_mem_operand_p (rtx); diff --git a/gcc/config/nds32/nds32-relax-opt.cc b/gcc/config/nds32/nds32-relax-opt.cc index 812ae1b04c98..594fb7b8b873 100644 --- a/gcc/config/nds32/nds32-relax-opt.cc +++ b/gcc/config/nds32/nds32-relax-opt.cc @@ -193,7 +193,7 @@ nds32_plus_reg_load_store_p (rtx_insn *insn) return false; } -/* Return true if x is const and the referance is ict symbol. */ +/* Return true if x is const and the reference is ict symbol. */ static bool nds32_ict_const_p (rtx x) { diff --git a/gcc/config/nds32/nds32-utils.cc b/gcc/config/nds32/nds32-utils.cc index e0f6ae486fb4..6470a8d83f77 100644 --- a/gcc/config/nds32/nds32-utils.cc +++ b/gcc/config/nds32/nds32-utils.cc @@ -369,7 +369,7 @@ extract_offset_rtx (rtx_insn *insn) rtx plus_rtx; rtx offset_rtx; - /* Find the MEM rtx. The multiple load/store insns doens't have + /* Find the MEM rtx. The multiple load/store insns doesn't have the offset field so we can return NULL_RTX here. */ switch (get_attr_type (insn)) { diff --git a/gcc/config/nds32/nds32.cc b/gcc/config/nds32/nds32.cc index 24ccca93e84a..4662812cf9bb 100644 --- a/gcc/config/nds32/nds32.cc +++ b/gcc/config/nds32/nds32.cc @@ -65,7 +65,7 @@ PART 3: Implement target hook stuff definitions. - PART 4: Implemet extern function definitions, + PART 4: Implement extern function definitions, the prototype is in nds32-protos.h. PART 5: Initialize target hook structure and definitions. */ @@ -237,7 +237,7 @@ static const char * const nds32_intrinsic_register_names[] = "$ITB" }; -/* Define instrinsic cctl names. */ +/* Define intrinsic cctl names. */ static const char * const nds32_cctl_names[] = { "L1D_VA_FILLCK", @@ -452,7 +452,7 @@ nds32_compute_stack_frame (void) cfun->machine->fp_size = (df_regs_ever_live_p (FP_REGNUM)) ? 4 : 0; /* If $gp value is required to be saved on stack, it needs 4 bytes space. - Check whether we are using PIC code genration. */ + Check whether we are using PIC code generation. */ cfun->machine->gp_size = (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) ? 4 : 0; @@ -500,8 +500,8 @@ nds32_compute_stack_frame (void) if (cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM) { /* Make first callee-saved number is even, - bacause we use doubleword access, and this way - promise 8-byte alignemt. */ + because we use doubleword access, and this way + promise 8-byte alignment. */ if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (r)) cfun->machine->callee_saved_first_fpr_regno = r - 1; else @@ -903,7 +903,7 @@ nds32_emit_stack_pop_multiple (unsigned Rb, unsigned Re, (set (reg:SI SP_REGNUM) (plus (reg:SI SP_REGNUM) (const_int 32)))]) */ - /* Calculate the number of registers that will be poped. */ + /* Calculate the number of registers that will be popped. */ extra_count = 0; if (save_fp_p) extra_count++; @@ -1177,8 +1177,8 @@ nds32_emit_stack_v3pop (unsigned Rb, (set (reg:SI SP_REGNUM) (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */ - /* Calculate the number of registers that will be poped. - Since $fp, $gp, and $lp is always poped with v3pop instruction, + /* Calculate the number of registers that will be popped. + Since $fp, $gp, and $lp is always popped with v3pop instruction, we need to count these three registers. Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. So there is no need to worry about Rb=Re=SP_REGNUM case. */ @@ -1768,7 +1768,7 @@ nds32_can_change_mode_class (machine_mode from, machine_mode to, reg_class_t rclass) { - /* Don't spill double-precision register to two singal-precision + /* Don't spill double-precision register to two single-precision registers */ if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) && GET_MODE_SIZE (from) != GET_MODE_SIZE (to)) @@ -1795,7 +1795,7 @@ nds32_can_change_mode_class (machine_mode from, 1. previous hard frame pointer 2. return address 3. callee-saved registers - 4. <padding bytes> (we will calculte in nds32_compute_stack_frame() + 4. <padding bytes> (we will calculate in nds32_compute_stack_frame() and save it at cfun->machine->callee_saved_area_padding_bytes) @@ -1813,7 +1813,7 @@ nds32_can_change_mode_class (machine_mode from, We 'wrap' these blocks together with hard frame pointer ($r28) and stack pointer ($r31). By applying the basic frame/stack/argument pointers concept, - the layout of a stack frame shoule be like this: + the layout of a stack frame should be like this: | | old stack pointer -> ---- @@ -1980,7 +1980,7 @@ nds32_arg_partial_bytes (cumulative_args_t ca, const function_arg_info &arg) if (TARGET_HARD_FLOAT) return 0; - /* If we have already runned out of argument registers, return zero + /* If we have already run out of argument registers, return zero so that the argument will be entirely pushed on the stack. */ if (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, arg.mode, arg.type) >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS) @@ -1997,7 +1997,7 @@ nds32_arg_partial_bytes (cumulative_args_t ca, const function_arg_info &arg) arg.mode, arg.type) - NDS32_GPR_ARG_FIRST_REGNUM); - /* Note that we have to return the nubmer of bytes, not registers count. */ + /* Note that we have to return the number of bytes, not registers count. */ if (needed_reg_count > remaining_reg_count) return remaining_reg_count * UNITS_PER_WORD; @@ -2321,7 +2321,7 @@ nds32_function_ok_for_sibcall (tree decl, because the stack layout may be a mess. 4. We don't want to apply sibling call optimization for indirect sibcall because the pop behavior in epilogue may pollute the - content of caller-saved regsiter when the register is used for + content of caller-saved register when the register is used for indirect sibcall. 5. In pic mode, it may use some registers for PLT call. */ return (!TARGET_V3PUSH @@ -3014,7 +3014,7 @@ nds32_register_move_cost (machine_mode mode, reg_class_t from, reg_class_t to) { - /* In garywolf cpu, FPR to GPR is chaper than other cpu. */ + /* In graywolf cpu, FPR to GPR is cheaper than other cpu. */ if (TARGET_PIPELINE_GRAYWOLF) { if (GET_MODE_SIZE (mode) == 8) @@ -3467,7 +3467,7 @@ nds32_print_operand (FILE *stream, rtx x, int code) else { /* If user applies normal way with __NDS32_REG_XXX__ enum data, - we can print out register name. Remember to substract 1024. */ + we can print out register name. Remember to subtract 1024. */ fprintf (stream, "%s", nds32_intrinsic_register_names[op_value - 1024]); } @@ -3920,7 +3920,7 @@ nds32_merge_decl_attributes (tree olddecl, tree newdecl) combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl), DECL_ATTRIBUTES (newdecl)); - /* Since newdecl is acutally a duplicate of olddecl, + /* Since newdecl is actually a duplicate of olddecl, we can take olddecl for some operations. */ if (TREE_CODE (olddecl) == FUNCTION_DECL) { @@ -3983,7 +3983,7 @@ nds32_insert_attributes (tree decl, tree *attributes) /* The following code may use attribute arguments. If there is no argument from source code, it will cause segmentation fault. - Therefore, return dircetly and report error message later. */ + Therefore, return directly and report error message later. */ if ((intr && TREE_VALUE (intr) == NULL) || (excp && TREE_VALUE (excp) == NULL) || (reset && TREE_VALUE (reset) == NULL)) @@ -4245,7 +4245,7 @@ nds32_init_libfuncs (void) /* ------------------------------------------------------------------------ */ -/* PART 4: Implemet extern function definitions, +/* PART 4: Implement extern function definitions, the prototype is in nds32-protos.h. */ /* Run-time Target Specification. */ @@ -5217,7 +5217,7 @@ nds32_expand_epilogue_v3pop (bool sibcall_p) /* We have to consider alloca issue as well. If the function does call alloca(), the stack pointer is not fixed. In that case, we cannot use 'pop25 Re,imm8u' directly. - We have to caculate stack pointer from frame pointer + We have to calculate stack pointer from frame pointer and then use 'pop25 Re,0'. Of course, the frame_pointer_needed should be nonzero if the function calls alloca(). */ @@ -5385,7 +5385,7 @@ nds32_can_use_return_insn (void) 1. This is a naked function. So there is no callee-saved, local size, or outgoing size. 2. This is NOT a variadic function. - So there is no pushing arguement registers into the stack. */ + So there is no pushing argument registers into the stack. */ return (cfun->machine->naked_p && (cfun->machine->va_args_size == 0)); } @@ -5421,7 +5421,7 @@ nds32_target_alignment (rtx_insn *label) /* Always align to 4 byte when first instruction after label is jump instruction since length for that might changed, so let's always align - it for make sure we don't lose any perfomance here. */ + it for make sure we don't lose any performance here. */ if (insn == 0 || (get_attr_length (insn) == 2 && !JUMP_P (insn) && !CALL_P (insn))) @@ -5495,7 +5495,7 @@ nds32_split_double_word_load_store_p(rtx *operands, bool load_p) if (optimize == 0 || !flag_schedule_insns_after_reload) return !satisfies_constraint_Da (mem) || MEM_VOLATILE_P (mem); - /* Split double word load store after copy propgation. */ + /* Split double word load store after copy propagation. */ if (current_pass == NULL) return false; diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h index 81f25ec84c52..e0b0bc33f0b0 100644 --- a/gcc/config/nds32/nds32.h +++ b/gcc/config/nds32/nds32.h @@ -1188,7 +1188,7 @@ enum nds32_builtins /* Register Classes. */ /* In nds32 target, we have three levels of registers: - Low cost regsiters : $r0 ~ $r7 + Low cost registers : $r0 ~ $r7 Middle cost registers : $r8 ~ $r11, $r16 ~ $r19 High cost registers : $r12 ~ $r14, $r20 ~ $r31 @@ -1689,7 +1689,7 @@ enum reg_class /* This is the machine mode that elements of a jump-table should have. */ #define CASE_VECTOR_MODE Pmode -/* Return the preferred mode for and addr_diff_vec when the mininum +/* Return the preferred mode for and addr_diff_vec when the minimum and maximum offset are known. */ #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body) \ nds32_case_vector_shorten_mode (min_offset, max_offset, body) diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md index d4da8aa72765..4b05c5f30a2a 100644 --- a/gcc/config/nds32/nds32.md +++ b/gcc/config/nds32/nds32.md @@ -642,7 +642,7 @@ (set_attr "length" "4")]) ;; divsr/divr will keep quotient only when quotient and remainder is the same -;; register in our ISA spec, it's can reduce 1 register presure if we don't +;; register in our ISA spec, it's can reduce 1 register pressure if we don't ;; want remainder. (define_insn "divsi4" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1574,7 +1574,7 @@ ) ;; Subroutine call instruction returning a value. -;; operands[0]: It is the hard regiser in which the value is returned. +;; operands[0]: It is the hard register in which the value is returned. ;; The rest three operands are the same as the ;; three operands of the 'call' instruction. ;; (but with numbers increased by one) @@ -2078,7 +2078,7 @@ ;; We are receiving operands from casesi pattern: ;; -;; operands[0]: The index that have been substracted with lower bound. +;; operands[0]: The index that have been subtracted with lower bound. ;; operands[1]: A label that precedes the table itself. ;; operands[2]: A temporary register to retrieve value in table. ;; diff --git a/gcc/config/nds32/nds32_intrinsic.h b/gcc/config/nds32/nds32_intrinsic.h index e8e527654375..755170303d03 100644 --- a/gcc/config/nds32/nds32_intrinsic.h +++ b/gcc/config/nds32/nds32_intrinsic.h @@ -33,7 +33,7 @@ typedef unsigned char uint8x4_t __attribute__ ((vector_size (4))); typedef unsigned short uint16x2_t __attribute__ ((vector_size (4))); typedef unsigned int uint32x2_t __attribute__((vector_size(8))); -/* General instrinsic register names. */ +/* General intrinsic register names. */ enum nds32_intrinsic_registers { __NDS32_REG_CPU_VER__ = 1024, diff --git a/gcc/config/nds32/nds32_isr.h b/gcc/config/nds32/nds32_isr.h index f686c9ba9ed1..5d80fd547409 100644 --- a/gcc/config/nds32/nds32_isr.h +++ b/gcc/config/nds32/nds32_isr.h @@ -434,7 +434,7 @@ typedef struct and software interrupt can be routed to any one of them. You may want to define your hardware interrupts in the following way - for easy maintainance. + for easy maintenance. IVIC mode: #define MY_HW_IVIC_TIMER NDS32_VECTOR_INTERRUPT_HW0 + 1 diff --git a/libgcc/config/nds32/initfini.c b/libgcc/config/nds32/initfini.c index a466bccf24ff..ac10c398f1c1 100644 --- a/libgcc/config/nds32/initfini.c +++ b/libgcc/config/nds32/initfini.c @@ -70,7 +70,7 @@ extern func_ptr __EH_FRAME_BEGIN__[]; /* Note that the following two functions are going to be chained into - constructor and destructor list, repectively. So these two declarations + constructor and destructor list, respectively. So these two declarations must be placed after __CTOR_LIST__ and __DTOR_LIST. */ extern void __nds32_register_eh(void) __attribute__((constructor, used)); extern void __nds32_deregister_eh(void) __attribute__((destructor, used)); diff --git a/libgcc/config/nds32/linux-atomic.c b/libgcc/config/nds32/linux-atomic.c index 8731e4380aa2..709a0879b421 100644 --- a/libgcc/config/nds32/linux-atomic.c +++ b/libgcc/config/nds32/linux-atomic.c @@ -24,7 +24,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see using the kernel helper defined below. There is no support for 64-bit operations yet. */ -/* This function copy form NDS32 Linux-kernal. */ +/* This function copy form NDS32 Linux-kernel. */ static inline int __kernel_cmpxchg (int oldval, int newval, int *mem) {
