https://gcc.gnu.org/g:fd928d34b63e7f7cca9b766785d6cacf6d84216f
commit r17-1105-gfd928d34b63e7f7cca9b766785d6cacf6d84216f Author: Dhruv Chawla <[email protected]> Date: Tue May 19 13:03:19 2026 +0000 gcn: Fix typos in various files Signed-off-by: Dhruv Chawla <[email protected]> gcc/ChangeLog: * config/gcn/constraints.md: Fix typos. * config/gcn/gcn-opts.h (TARGET_ARCHITECTED_FLAT_SCRATCH): Likewise. * config/gcn/gcn-valu.md: Likewise. * config/gcn/gcn.cc (gcn_gen_undef): Likewise. (gcn_addr_space_debug): Likewise. (gcn_expand_prologue): Likewise. (gcn_frame_pointer_rqd): Likewise. * config/gcn/gcn.h (NUM_PARM_REGS): Likewise. (enum gcn_builtin_codes): Likewise. * config/gcn/gcn.md: Likewise. Diff: --- gcc/config/gcn/constraints.md | 10 +++++----- gcc/config/gcn/gcn-opts.h | 2 +- gcc/config/gcn/gcn-valu.md | 2 +- gcc/config/gcn/gcn.cc | 20 ++++++++++---------- gcc/config/gcn/gcn.h | 4 ++-- gcc/config/gcn/gcn.md | 8 ++++---- 6 files changed, 23 insertions(+), 23 deletions(-) diff --git a/gcc/config/gcn/constraints.md b/gcc/config/gcn/constraints.md index c683af420a33..4c3317a821d0 100644 --- a/gcc/config/gcn/constraints.md +++ b/gcc/config/gcn/constraints.md @@ -28,7 +28,7 @@ (match_test "((unsigned HOST_WIDE_INT) ival + 0x8000) < 0x10000"))) (define_constraint "Kf" - "Immeditate constant -1" + "Immediate constant -1" (and (match_code "const_int") (match_test "ival == -1"))) @@ -84,16 +84,16 @@ "SGPR registers") (define_register_constraint "SD" "SGPR_DST_REGS" - "registers useable as a destination of scalar operation") + "registers usable as a destination of scalar operation") (define_register_constraint "SS" "SGPR_SRC_REGS" - "registers useable as a source of scalar operation") + "registers usable as a source of scalar operation") (define_register_constraint "Sm" "SGPR_MEM_SRC_REGS" - "registers useable as a source of scalar memory operation") + "registers usable as a source of scalar memory operation") (define_register_constraint "Sv" "SGPR_VOP_SRC_REGS" - "registers useable as a source of VOP3A instruction") + "registers usable as a source of VOP3A instruction") (define_register_constraint "ca" "ALL_CONDITIONAL_REGS" "SCC VCCZ or EXECZ") diff --git a/gcc/config/gcn/gcn-opts.h b/gcc/config/gcn/gcn-opts.h index 45bc5783f2a4..d771e788e31d 100644 --- a/gcc/config/gcn/gcn-opts.h +++ b/gcc/config/gcn/gcn-opts.h @@ -104,7 +104,7 @@ enum hsaco_attr_type : 4) /* This mostly affects the metadata. */ #define TARGET_ARCHITECTED_FLAT_SCRATCH (TARGET_RDNA3 || TARGET_CDNA3) -/* Device has Sub-DWord Addressing instrucions. */ +/* Device has Sub-DWord Addressing instructions. */ #define TARGET_SDWA (!TARGET_RDNA3) /* Different devices uses different cache control instructions. */ #define TARGET_WBINVL1_CACHE (!TARGET_RDNA2_PLUS && !TARGET_CDNA3) diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 9d752c717ffe..253d13279c0e 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -4417,7 +4417,7 @@ ;; Warning: This "-ffast-math" implementation converts in-order reductions ;; into associative reductions. It's also used where OpenMP or -;; OpenACC paralellization has already broken the in-order semantics. +;; OpenACC parallelization has already broken the in-order semantics. (define_expand "fold_left_plus_<mode>" [(match_operand:<SCALAR_MODE> 0 "register_operand") (match_operand:<SCALAR_MODE> 1 "gcn_alu_operand") diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc index 4ba767c6951c..18995d61e7be 100644 --- a/gcc/config/gcn/gcn.cc +++ b/gcc/config/gcn/gcn.cc @@ -1242,7 +1242,7 @@ gcn_gen_undef (machine_mode mode) /* {{{ Utility functions. */ /* Generalised accessor functions for instruction patterns. - The machine desription '@' prefix does something similar, but as of + The machine description '@' prefix does something similar, but as of GCC 10 is incompatible with define_subst, and anyway it doesn't auto-handle the exec feature. @@ -1956,7 +1956,7 @@ gcn_addr_space_debug (addr_space_t as) /* Implement REGNO_MODE_CODE_OK_FOR_BASE_P via gcn.h - Retun true if REGNO is OK for memory adressing. */ + Return true if REGNO is OK for memory addressing. */ bool gcn_regno_mode_code_ok_for_base_p (int regno, @@ -3395,8 +3395,8 @@ gcn_expand_prologue () + offsets->local_vars + offsets->outgoing_args_size; if (sp_adjust > 0) { - /* Adding RTX_FRAME_RELATED_P effectively disables spliting, so - we use split add explictly, and specify the DImode add in + /* Adding RTX_FRAME_RELATED_P effectively disables splitting, so + we use split add explicitly, and specify the DImode add in the note. */ rtx scc = gen_rtx_REG (BImode, SCC_REG); rtx adjustment = gen_int_mode (sp_adjust, SImode); @@ -3415,8 +3415,8 @@ gcn_expand_prologue () if (offsets->need_frame_pointer) { - /* Adding RTX_FRAME_RELATED_P effectively disables spliting, so - we use split add explictly, and specify the DImode add in + /* Adding RTX_FRAME_RELATED_P effectively disables splitting, so + we use split add explicitly, and specify the DImode add in the note. */ rtx scc = gen_rtx_REG (BImode, SCC_REG); int fp_adjust = -(offsets->local_vars + offsets->outgoing_args_size); @@ -3446,7 +3446,7 @@ gcn_expand_prologue () { if (TARGET_PACKED_WORK_ITEMS) { - /* v0 conatins the X, Y and Z dimensions all in one. + /* v0 contains the X, Y and Z dimensions all in one. Expand them out for ABI compatibility. */ /* TODO: implement and use zero_extract. */ rtx v1 = gen_rtx_REG (V64SImode, VGPR_REGNO (1)); @@ -3540,8 +3540,8 @@ gcn_expand_prologue () emit_insn (gen_addsi3_scalar_carry (fp_lo, fp_lo, wave_offset, scc)); emit_insn (gen_addcsi3_scalar_zero (fp_hi, fp_hi, scc)); - /* Adding RTX_FRAME_RELATED_P effectively disables spliting, so we use - split add explictly, and specify the DImode add in the note. + /* Adding RTX_FRAME_RELATED_P effectively disables splitting, so we use + split add explicitly, and specify the DImode add in the note. The DWARF info expects that the callee-save data is in the frame, even though it isn't (because this is the entry point), so we make a notional adjustment to the DWARF frame offset here. */ @@ -3680,7 +3680,7 @@ gcn_frame_pointer_rqd (void) { /* GDB needs the frame pointer in order to unwind properly, but that's not important for the entry point, unless alloca is used. - It's not important for code execution, so we should repect the + It's not important for code execution, so we should respect the -fomit-frame-pointer flag. */ return (!flag_omit_frame_pointer && cfun diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h index f0c778372c59..b02cbdb70826 100644 --- a/gcc/config/gcn/gcn.h +++ b/gcc/config/gcn/gcn.h @@ -216,7 +216,7 @@ STATIC_ASSERT (LAST_AVGPR_REG + 1 - FIRST_AVGPR_REG == 256); #define NUM_PARM_REGS 6 /* There is no arg pointer. Just choose random fixed register that does - not intefere with anything. */ + not interfere with anything. */ #define ARG_POINTER_REGNUM SOFT_ARG_REG #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 @@ -865,7 +865,7 @@ enum gcn_builtin_codes /* Costs. */ -/* Branches are to be dicouraged when theres an alternative. +/* Branches are to be dicouraged when there's an alternative. FIXME: This number is plucked from the air. */ #define BRANCH_COST(SPEED_P, PREDICABLE_P) 10 diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index c49bd6cf8bd2..f95e7e555c9e 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -98,7 +98,7 @@ ; ; sop2 - scalar, two inputs, one output ; ssrc0/ssrc1: sgpr 0-102; flat_scratch,xnack,vcc,tba,tma,ttmp0-11,exec -; vccz,execz,scc,inline immedate,fp inline immediate +; vccz,execz,scc,inline immediate,fp inline immediate ; sdst: sgpr 0-102; flat_scratch,xnack,vcc,tba,tma,ttmp0-11,exec ; ; Constraints "=SD, SD", "SSA,SSB","SSB,SSA" @@ -115,7 +115,7 @@ ; ; Constraints "=SD", "SSA" ; -; sopc - scalar, two inputs, one comparsion +; sopc - scalar, two inputs, one comparison ; ssrc0: same as sop2/ssc0. ; ; Constraints "SSI,SSA","SSA,SSI" @@ -147,7 +147,7 @@ ; ; constraints: "=v", "vBSv" ; -; vopc - vector, two inputs, one comparsion output; +; vopc - vector, two inputs, one comparison output; ; vsrc0: same as vop2/src0 ; vsrc1: vgpr0-255 ; vdst: @@ -1915,7 +1915,7 @@ ; into the L1 cache, this is not actually safe. ; ; Additionally, scalar flat instructions access L2 via a different cache -; (the "constant cache"), so they have separate constrol instructions. We +; (the "constant cache"), so they have separate control instructions. We ; do not attempt to invalidate both caches at once; instead, atomics ; operating on scalar flat pointers will flush the constant cache, and ; atomics operating on flat or global pointers will flush L1. It is up to
