https://gcc.gnu.org/g:9c31ebe3a2019d802a4aceb556321becf9b7abec
commit r17-1111-g9c31ebe3a2019d802a4aceb556321becf9b7abec Author: Dhruv Chawla <[email protected]> Date: Wed May 20 11:40:33 2026 +0000 mips: Fix typos in various files Signed-off-by: Dhruv Chawla <[email protected]> gcc/ChangeLog: * config/mips/driver-native.cc (host_detect_local_cpu): Fix typos. * config/mips/mips-cpus.def (MIPS_CPU): Likewise. * config/mips/mips.cc (mips_setup_incoming_varargs): Likewise. (mips_function_ok_for_sibcall): Likewise. (mips_expand_ext_as_unaligned_load): Likewise. (mips_use_ins_ext_p): Likewise. (mips_pop_asm_switch): Likewise. (mips_cfun_has_inflexible_gp_ref_p): Likewise. (mips_set_compression_mode): Likewise. (mips_expand_vec_unpack): Likewise. * config/mips/mips.h (while): Likewise. * config/mips/mips.md: Likewise. libgcc/ChangeLog: * config/mips/linux-unwind.h (mips_fallback_frame_state): Likewise. Diff: --- gcc/config/mips/driver-native.cc | 2 +- gcc/config/mips/mips-cpus.def | 2 +- gcc/config/mips/mips.cc | 20 ++++++++++---------- gcc/config/mips/mips.h | 2 +- gcc/config/mips/mips.md | 4 ++-- libgcc/config/mips/linux-unwind.h | 2 +- 6 files changed, 16 insertions(+), 16 deletions(-) diff --git a/gcc/config/mips/driver-native.cc b/gcc/config/mips/driver-native.cc index 3311b84dbd31..db07763ee77a 100644 --- a/gcc/config/mips/driver-native.cc +++ b/gcc/config/mips/driver-native.cc @@ -44,7 +44,7 @@ const char * host_detect_local_cpu (int argc, const char **argv) { const char *cpu = NULL; - /* Don't assigne any static string to ret. If you need to do so, + /* Don't assign any static string to ret. If you need to do so, use concat. */ char *ret = NULL; char buf[128]; diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 973fd26c19c9..4783cf32ab6e 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -44,7 +44,7 @@ MIPS_CPU ("mips4", PROCESSOR_R10000, MIPS_ISA_MIPS4, PTF_AVOID_BRANCHLIKELY_SIZE isn't tuned to a specific processor. */ MIPS_CPU ("mips32", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32, PTF_AVOID_BRANCHLIKELY_ALWAYS) MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, MIPS_ISA_MIPS32R2, PTF_AVOID_BRANCHLIKELY_ALWAYS) -/* mips32r3 is micromips hense why it uses the M4K processor. */ +/* mips32r3 is micromips hence why it uses the M4K processor. */ MIPS_CPU ("mips32r3", PROCESSOR_M4K, MIPS_ISA_MIPS32R3, PTF_AVOID_BRANCHLIKELY_ALWAYS) MIPS_CPU ("mips32r5", PROCESSOR_P5600, MIPS_ISA_MIPS32R5, PTF_AVOID_BRANCHLIKELY_ALWAYS) MIPS_CPU ("mips32r6", PROCESSOR_I6400, MIPS_ISA_MIPS32R6, 0) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index cc45a195b891..303766db5229 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -512,7 +512,7 @@ static const char *mips_base_align_functions; /* align_functions */ /* Index [M][R] is true if register R is allowed to hold a value of mode M. */ static bool mips_hard_regno_mode_ok_p[MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; -/* Index C is true if character C is a valid PRINT_OPERAND punctation +/* Index C is true if character C is a valid PRINT_OPERAND punctuation character. */ static bool mips_print_operand_punct[256]; @@ -6987,8 +6987,8 @@ mips_setup_incoming_varargs (cumulative_args_t cum, local_cum = *get_cumulative_args (cum); /* For a C23 variadic function w/o any named argument, and w/o an - artifical argument for large return value, skip advancing args. - There is such an artifical argument iff. arg.type is non-NULL + artificial argument for large return value, skip advancing args. + There is such an artificial argument iff. arg.type is non-NULL (PR 114175). */ if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl)) || arg.type != NULL_TREE) @@ -8360,7 +8360,7 @@ mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) return false; /* Direct Js are only possible to functions that use the same ISA encoding. - There is no JX counterpoart of JALX. */ + There is no JX counterpart of JALX. */ if (decl && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode) && mips_call_may_need_jalx_p (decl)) @@ -8880,7 +8880,7 @@ mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width, } /* If we were loading 32bits and the original register was DI then - sign/zero extend into the orignal dest. */ + sign/zero extend into the original dest. */ if (dest1) { if (unsigned_p) @@ -8977,7 +8977,7 @@ mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos) } /* Check if MASK and SHIFT are valid in mask-low-and-shift-left - operation if MAXLEN is the maxium length of consecutive bits that + operation if MAXLEN is the maximum length of consecutive bits that can make up MASK. MODE is the mode of the operation. See mask_low_and_shift_len for the actual definition. */ @@ -9237,7 +9237,7 @@ mips_pop_asm_switch (struct mips_asm_switch *asm_switch) mips_pop_asm_switch_1 (asm_switch, "\t", "\n"); } -/* Print the text for PRINT_OPERAND punctation character CH to FILE. +/* Print the text for PRINT_OPERAND punctuation character CH to FILE. The punctuation characters are: '(' Start a nested ".set noreorder" block. @@ -11036,7 +11036,7 @@ mips_cfun_has_inflexible_gp_ref_p (void) return true; /* MIPS16 functions that return in FPRs need to call an - external libgcc routine. This call is only made explict + external libgcc routine. This call is only made explicit during mips_expand_epilogue, and it too might be lazily bound. */ if (mips16_cfun_returns_in_fpr_p ()) return true; @@ -20219,7 +20219,7 @@ mips_set_compression_mode (unsigned int compression_mode) /* Don't move loop invariants, because it tends to increase register pressure. It also introduces an extra move in cases where the constant is the first operand in a two-operand binary - instruction, or when it forms a register argument to a functon + instruction, or when it forms a register argument to a function call. */ flag_move_loop_invariants = 0; @@ -22384,7 +22384,7 @@ mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p) if (!unsigned_p) { - /* Extract sign extention for each element comparing each element + /* Extract sign extension for each element comparing each element with immediate zero. */ tmp = gen_reg_rtx (imode); emit_insn (cmpFunc (tmp, operands[1], CONST0_RTX (imode))); diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index c461d8aea3d4..48a562f2d39d 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -2982,7 +2982,7 @@ while (0) ... .uleb128 foo-$LFBxxx - The .uleb128 requies $LFBxxx to match the FDE start address, which is + The .uleb128 requires $LFBxxx to match the FDE start address, which is likewise a byte pointer rather than an ISA-encoded address. At the time of writing, this hook is not used for the function end diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 85e7d67901f7..18244e4abcc8 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -7056,7 +7056,7 @@ ;; from being computed before an earlier call. To do this, we: ;; ;; - Ensure that the register is live on entry to the function, -;; so that it is never thought to be used uninitalized. +;; so that it is never thought to be used uninitialized. ;; ;; - Ensure that the register is live on exit from the function, ;; so that it is live throughout. @@ -7842,7 +7842,7 @@ ;; accessible in MIPS16. ;; ;; This is not represented as a call insn, to avoid the -;; unnecesarry clobbering of caller-save registers by a +;; unnecessary clobbering of caller-save registers by a ;; function consisting only of: "rdhwr $3,$29; j $31; nop;" ;; ;; A $25 clobber is added to cater for a $25 load stub added by the diff --git a/libgcc/config/mips/linux-unwind.h b/libgcc/config/mips/linux-unwind.h index 43d6f690dc10..9fa7de58228b 100644 --- a/libgcc/config/mips/linux-unwind.h +++ b/libgcc/config/mips/linux-unwind.h @@ -113,7 +113,7 @@ mips_fallback_frame_state (struct _Unwind_Context *context, address of the second byte of the faulting instruction. Note that setting fs->signal_frame would not work. As the comment - above MASK_RETURN_ADDR explains, MIPS unwinders must earch for an + above MASK_RETURN_ADDR explains, MIPS unwinders must search for an odd-valued address. */ fs->regs.how[__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__] = REG_SAVED_VAL_OFFSET;
