https://gcc.gnu.org/g:02b234aba6609b137ddb5e471b550a31cee9ad48
commit r17-1224-g02b234aba6609b137ddb5e471b550a31cee9ad48 Author: Wang Yaduo <[email protected]> Date: Tue Jun 2 07:12:54 2026 -0600 [PATCH] RISC-V: Add tuning info and vector cost model for xt-c9501fdvt Switch the xt-c9501fdvt RISCV_TUNE entry from generic_ooo_tune_info to a new xt_c9501_tune_info, with its own scalar tuning parameters and a dedicated cpu_vector_cost table (xt_c9501_vector_cost) covering VLS / VLA per-type statement, load/store and reduction costs. gcc/ChangeLog: * config/riscv/riscv-cores.def: Switch xt-c9501fdvt tune to xt_c9501_tune_info. * config/riscv/riscv.cc (xt_c9501_vls_vector_cost): New. (xt_c9501_vla_vector_cost): New. (xt_c9501_vector_cost): New. (xt_c9501_tune_info): New. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-vect-stmt-cost.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-vect-ldst-cost.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-reduc-unordered.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-reduc-ordered.c: New test. Diff: --- gcc/config/riscv/riscv-cores.def | 2 +- gcc/config/riscv/riscv.cc | 71 ++++++++++++++++++++++ .../riscv/rvv/xt-c9501fdvt-reduc-ordered.c | 23 +++++++ .../riscv/rvv/xt-c9501fdvt-reduc-unordered.c | 29 +++++++++ .../riscv/rvv/xt-c9501fdvt-vect-ldst-cost.c | 14 +++++ .../riscv/rvv/xt-c9501fdvt-vect-stmt-cost.c | 20 ++++++ 6 files changed, 158 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 99d5963d14c8..416fcacdd0b7 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -48,7 +48,7 @@ RISCV_TUNE("xt-c910", generic, generic_ooo_tune_info) RISCV_TUNE("xt-c910v2", generic, generic_ooo_tune_info) RISCV_TUNE("xt-c920", generic, generic_ooo_tune_info) RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info) -RISCV_TUNE("xt-c9501fdvt", generic_ooo, generic_ooo_tune_info) +RISCV_TUNE("xt-c9501fdvt", generic_ooo, xt_c9501_tune_info) RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info) RISCV_TUNE("xiangshan-kunminghu", xiangshan, generic_ooo_tune_info) RISCV_TUNE("spacemit-x60", spacemit_x60, spacemit_x60_tune_info) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 13c8378c4de6..a2730a90ca8b 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -665,6 +665,77 @@ static const struct riscv_tune_param generic_ooo_tune_info = { true, /* prefer-agnostic. */ }; +static const common_vector_cost xt_c9501_vls_vector_cost = { + 3, /* int_stmt_cost */ + 4, /* fp_stmt_cost */ + 99, /* gather_load_cost */ + 32, /* scatter_store_cost */ + 8, /* segment_permute (2) */ + 9, /* segment_permute (3) */ + 9, /* segment_permute (4) */ + 12, /* segment_permute (5) */ + 12, /* segment_permute (6) */ + 12, /* segment_permute (7) */ + 12, /* segment_permute (8) */ + 2, /* vec_to_scalar_cost */ + 2, /* scalar_to_vec_cost */ + 4, /* permute_cost */ + 6, /* align_load_cost */ + 1, /* align_store_cost */ + 8, /* unalign_load_cost */ + 2, /* unalign_store_cost */ + 6, /* reduc_i8_cost */ + 6, /* reduc_i16_cost */ + 6, /* reduc_i32_cost */ + 6, /* reduc_i64_cost */ + 11, /* reduc_f16_cost */ + 11, /* reduc_f32_cost */ + 9, /* reduc_f64_cost */ + 17, /* reduc_f16_ordered_cost */ + 16, /* reduc_f32_ordered_cost */ + 12, /* reduc_f64_ordered_cost */ +}; + +static const scalable_vector_cost + xt_c9501_vla_vector_cost (xt_c9501_vls_vector_cost); + +static const struct cpu_vector_cost xt_c9501_vector_cost = { + 1, /* scalar_int_stmt_cost */ + 2, /* scalar_fp_stmt_cost */ + 4, /* scalar_load_cost */ + 1, /* scalar_store_cost */ + 1, /* cond_taken_branch_cost */ + 1, /* cond_not_taken_branch_cost */ + &xt_c9501_vls_vector_cost, /* vls */ + &xt_c9501_vla_vector_cost, /* vla */ + &rvv_regmove_vector_cost, /* regmove */ +}; + +/* Costs to use when optimizing for XT C9501. */ +static const struct riscv_tune_param xt_c9501_tune_info = { + {COSTS_N_INSNS (2), COSTS_N_INSNS (2)}, /* fp_add */ + {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* fp_mul */ + {COSTS_N_INSNS (8), COSTS_N_INSNS (13)}, /* fp_div */ + {COSTS_N_INSNS (2), COSTS_N_INSNS (2)}, /* int_mul */ + {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* int_div */ + 8, /* issue_rate */ + 2, /* branch_cost */ + 5, /* memory_cost */ + 2, /* fmv_cost */ + false, /* slow_unaligned_access */ + false, /* vector_unaligned_access */ + true, /* use_divmod_expansion */ + false, /* overlap_op_by_pieces */ + true, /* use_zero_stride_load */ + false, /* speculative_sched_vsetvl */ + RISCV_FUSE_NOTHING, /* fusible_ops */ + &xt_c9501_vector_cost, /* vector cost */ + "32", /* function_align */ + "8", /* jump_align */ + "16", /* loop_align */ + true, /* prefer-agnostic. */ +}; + /* Costs to use when optimizing for Tenstorrent Ascalon 8 wide. */ static const struct riscv_tune_param tt_ascalon_d8_tune_info = { {COSTS_N_INSNS (2), COSTS_N_INSNS (2)}, /* fp_add */ diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-reduc-ordered.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-reduc-ordered.c new file mode 100644 index 000000000000..87d2a77fde6a --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-reduc-ordered.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -mcpu=xt-c9501fdvt -O3 -mrvv-vector-bits=scalable -fvect-cost-model=unlimited -fdump-tree-vect-details" } */ + +#include <stdint-gcc.h> + +#define DEF_REDUC_PLUS(TYPE) \ + TYPE __attribute__ ((noinline, noclone)) \ + reduc_plus_##TYPE (TYPE *restrict a, int n) \ + { \ + TYPE r = 0; \ + for (int i = 0; i < n; ++i) \ + r += a[i]; \ + return r; \ + } + +DEF_REDUC_PLUS (_Float16) +DEF_REDUC_PLUS (float) +DEF_REDUC_PLUS (double) + +/* { dg-final { scan-assembler {vfredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} } } */ +/* { dg-final { scan-tree-dump "vec_to_scalar costs 19 in body" "vect" } } */ +/* { dg-final { scan-tree-dump "vec_to_scalar costs 18 in body" "vect" } } */ +/* { dg-final { scan-tree-dump "vec_to_scalar costs 14 in body" "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-reduc-unordered.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-reduc-unordered.c new file mode 100644 index 000000000000..7c86c2dae987 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-reduc-unordered.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -mcpu=xt-c9501fdvt -O3 -mrvv-vector-bits=scalable -ffast-math -fvect-cost-model=unlimited -fdump-tree-vect-details" } */ + +#include <stdint-gcc.h> + +#define DEF_REDUC_PLUS(TYPE) \ +TYPE __attribute__ ((noinline, noclone)) \ +reduc_plus_##TYPE (TYPE *restrict a, int n) \ +{ \ + TYPE r = 0; \ + for (int i = 0; i < n; ++i) \ + r += a[i]; \ + return r; \ +} + +DEF_REDUC_PLUS (int8_t) +DEF_REDUC_PLUS (int16_t) +DEF_REDUC_PLUS (int32_t) +DEF_REDUC_PLUS (int64_t) +DEF_REDUC_PLUS (_Float16) +DEF_REDUC_PLUS (float) +DEF_REDUC_PLUS (double) + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 7 "vect" } } */ +/* { dg-final { scan-assembler-times {vredsum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {vfredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */ +/* { dg-final { scan-tree-dump "vec_to_scalar costs 8 in epilogue" "vect" } } */ +/* { dg-final { scan-tree-dump "vec_to_scalar costs 13 in epilogue" "vect" } } */ +/* { dg-final { scan-tree-dump "vec_to_scalar costs 11 in epilogue" "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-vect-ldst-cost.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-vect-ldst-cost.c new file mode 100644 index 000000000000..3b56c835512c --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-vect-ldst-cost.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -mcpu=xt-c9501fdvt -O3 -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ + +void +add1_i32 (int *restrict a, int *restrict b, int n) +{ + /* b[i] + 1 prevents the loop from being recognised as memcpy. */ + for (int i = 0; i < n; ++i) + a[i] = b[i] + 1; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 1 "vect" } } */ +/* { dg-final { scan-tree-dump "vector_load costs 6 in body" "vect" } } */ +/* { dg-final { scan-tree-dump "vector_store costs 1 in body" "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-vect-stmt-cost.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-vect-stmt-cost.c new file mode 100644 index 000000000000..fc9e6040ec9b --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/xt-c9501fdvt-vect-stmt-cost.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -mcpu=xt-c9501fdvt -O3 -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ + +void +add_i32 (int *restrict a, int *restrict b, int n) +{ + for (int i = 0; i < n; ++i) + a[i] += b[i]; +} + +void +add_f32 (float *restrict a, float *restrict b, int n) +{ + for (int i = 0; i < n; ++i) + a[i] += b[i]; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-tree-dump "vector_stmt costs 3 in body" "vect" } } */ +/* { dg-final { scan-tree-dump "vector_stmt costs 4 in body" "vect" } } */
