https://gcc.gnu.org/g:8bef821de3b31cda42c3b8a37008a7ea598c6c6c
commit r17-1226-g8bef821de3b31cda42c3b8a37008a7ea598c6c6c Author: Lino Hsing-Yu Peng <[email protected]> Date: Tue Jun 2 07:37:22 2026 -0600 [PATCH 1/8] RISC-V: Add zvfofp8min ISA extension support Add initial ISA-level for Zvfofp8min extension. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zvfofp8min support. * config/riscv/riscv-ext.def: Add zvfofp8min entry. * config/riscv/riscv-ext.opt: Add zvfofp8min option. * config/riscv/riscv-vector-builtins.cc: Require zvfofp8min. * config/riscv/riscv-vector-builtins.h: Add zvfofp8min handling. * doc/riscv-ext.texi: Document the new extension. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-61.c: New test. Diff: --- gcc/common/config/riscv/riscv-common.cc | 2 ++ gcc/config/riscv/riscv-ext.def | 13 +++++++++++++ gcc/config/riscv/riscv-ext.opt | 3 ++- gcc/config/riscv/riscv-vector-builtins.cc | 2 ++ gcc/config/riscv/riscv-vector-builtins.h | 7 +++++++ gcc/doc/riscv-ext.texi | 4 ++++ gcc/testsuite/gcc.target/riscv/arch-61.c | 5 +++++ 7 files changed, 35 insertions(+), 1 deletion(-) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index e483e2bdd79b..20f40fc662c7 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -1484,6 +1484,8 @@ static const riscv_extra_ext_flag_table_t riscv_extra_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("zvfbfwma", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_BF_16), RISCV_EXT_FLAG_ENTRY ("zvfhmin", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16), RISCV_EXT_FLAG_ENTRY ("zvfh", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16), + RISCV_EXT_FLAG_ENTRY ("zvfofp8min", x_riscv_vector_elen_flags, + MASK_VECTOR_ELEN_FP_32), RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32), RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64), diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def index efdb510ce60a..b9ef0c5ea057 100644 --- a/gcc/config/riscv/riscv-ext.def +++ b/gcc/config/riscv/riscv-ext.def @@ -1169,6 +1169,19 @@ DEFINE_RISCV_EXT( /* BITMASK_BIT_POSITION*/ 18, /* EXTRA_EXTENSION_FLAGS */ 0) +DEFINE_RISCV_EXT( + /* NAME */ zvfofp8min, + /* UPPERCASE_NAME */ ZVFOFP8MIN, + /* FULL_NAME */ "Vector FP8 minimum extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32f"}), + /* SUPPORTED_VERSIONS */ ({{0, 2}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + DEFINE_RISCV_EXT( /* NAME */ zvfbfwma, /* UPPERCASE_NAME */ ZVFBFWMA, diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt index 472dabf8a936..802c9eb41706 100644 --- a/gcc/config/riscv/riscv-ext.opt +++ b/gcc/config/riscv/riscv-ext.opt @@ -266,6 +266,8 @@ Mask(ZVE64X) Var(riscv_zve_subext) Mask(ZVFBFMIN) Var(riscv_zvf_subext) +Mask(ZVFOFP8MIN) Var(riscv_zvf_subext) + Mask(ZVFBFWMA) Var(riscv_zvf_subext) Mask(ZVFH) Var(riscv_zvf_subext) @@ -473,4 +475,3 @@ Mask(XANDESVPACKFPH) Var(riscv_xandes_subext) Mask(XANDESVDOT) Var(riscv_xandes_subext) Mask(XSMTVDOT) Var(riscv_xsmt_subext) - diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index b8be45ed942c..0fcc60b59421 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -3654,6 +3654,8 @@ get_builtin_partition (required_ext ext, const function_instance &instance) return RVV_PARTITION_ZVFBFMIN; case ZVFBFWMA_EXT: return RVV_PARTITION_ZVFBFWMA; + case ZVFOFP8MIN_EXT: + return RVV_PARTITION_ZVFOFP8MIN; case XSFVQMACCQOQ_EXT: return RVV_PARTITION_XSFVQMACCQOQ; case XSFVQMACCDOD_EXT: diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index 8d6473f48375..aa20cb82c483 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -110,6 +110,7 @@ static const unsigned int CP_WRITE_CSR = 1U << 5; #define RVV_REQUIRE_MIN_VLEN_64 (1 << 5) /* Require TARGET_MIN_VLEN >= 64. */ #define RVV_REQUIRE_ELEN_FP_16 (1 << 6) /* Require FP ELEN >= 32. */ #define RVV_REQUIRE_ELEN_BF_16 (1 << 7) /* Require BF16. */ +#define RVV_REQUIRE_ZVFOFP8MIN (1 << 8) /* Require ZVFOFP8MIN extension. */ /* Enumerates the required extensions. */ enum required_ext @@ -129,6 +130,7 @@ enum required_ext ZVKSH_EXT, /* Crypto vector Zvksh sub-ext */ ZVFBFMIN_EXT, /* Zvfbfmin extension */ ZVFBFWMA_EXT, /* Zvfbfwma extension */ + ZVFOFP8MIN_EXT, /* Zvfofp8min extension */ XSFVQMACCQOQ_EXT, /* XSFVQMACCQOQ extension */ XSFVQMACCDOD_EXT, /* XSFVQMACCDOD extension */ XSFVFNRCLIPXFQF_EXT, /* XSFVFNRCLIPXFQF extension */ @@ -159,6 +161,7 @@ enum rvv_builtin_partition RVV_PARTITION_ZVFBFWMA, RVV_PARTITION_ZVFHMIN, RVV_PARTITION_ZVFH, + RVV_PARTITION_ZVFOFP8MIN, RVV_PARTITION_XSFVQMACCQOQ, RVV_PARTITION_XSFVQMACCDOD, RVV_PARTITION_XSFVFNRCLIPXFQF, @@ -211,6 +214,8 @@ static inline const char * required_ext_to_isa_name (enum required_ext required) return "zvfbfmin"; case ZVFBFWMA_EXT: return "zvfbfwma"; + case ZVFOFP8MIN_EXT: + return "zvfofp8min"; case XSFVQMACCQOQ_EXT: return "xsfvqmaccqoq"; case XSFVQMACCDOD_EXT: @@ -266,6 +271,8 @@ static inline bool required_extensions_specified (enum required_ext required) return TARGET_ZVFBFMIN; case ZVFBFWMA_EXT: return TARGET_ZVFBFWMA; + case ZVFOFP8MIN_EXT: + return TARGET_ZVFOFP8MIN; case XSFVQMACCQOQ_EXT: return TARGET_XSFVQMACCQOQ; case XSFVQMACCDOD_EXT: diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi index dd00dc154be4..728cde737a7c 100644 --- a/gcc/doc/riscv-ext.texi +++ b/gcc/doc/riscv-ext.texi @@ -338,6 +338,10 @@ @tab 1.0 @tab Vector BF16 converts extension +@item @samp{zvfofp8min} +@tab 0.2 +@tab Vector FP8 minimum extension + @item @samp{zvfbfwma} @tab 1.0 @tab Vector BF16 widening multiply/add extension diff --git a/gcc/testsuite/gcc.target/riscv/arch-61.c b/gcc/testsuite/gcc.target/riscv/arch-61.c new file mode 100644 index 000000000000..921a43cebd64 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-61.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvfofp8min -mabi=lp64" } */ +int +foo () +{}
