https://gcc.gnu.org/g:44a371a5b3c4fee7b3085a0d21292c794cbca774
commit r17-1243-g44a371a5b3c4fee7b3085a0d21292c794cbca774 Author: Jin Ma <[email protected]> Date: Tue Jun 2 21:38:43 2026 +0800 RISC-V: Remove dead code in riscv_sched_reorder While investigating vsetvl ping-ponging cases recently, the ready queue reordering hook riscv_sched_reorder was found to contain an unconditional return that makes most of the body unreachable: if (!last_vconfig.valid || *nreadyp == 1) return riscv_issue_rate (); return riscv_issue_rate (); /* dead, kills reordering below. */ int nready = *nreadyp; ... The hook was introduced by commit 63632889651 ("[RISC-V] Reorder ready queue slightly to avoid unnecessary vsetvl instructions"). It is unclear whether the second return was intentional (e.g. left as a temporary guard) or a leftover. Either way, since the surrounding code is specifically designed to group instructions with the same vector configuration and reduce vsetvl ping-ponging, the dead return defeats the hook's stated purpose. Remove the dead return so the reordering can actually run. A quick look at the resulting fallout is benign: re-enabling the reordering changes the vsetvl emission pattern for the zve64f testcases pr111037-1.c, pr111037-4.c and pr113248.c. The reorder now places vle64.v + vadd.vv (both with mode-derived SEW=64) before vfmv.s.f (SEW=16), so the vsetvl pass emits vsetivli zero, 1, e64, m1 ... vsetivli zero, 1, e16, m1 instead of the prior vsetivli zero, 1, e16, mf4 ... vsetvli zero, zero, e64, m1 Both sequences contain two vsetvl insns, so the total switching cost is unchanged. Updating the scan-assembler-times patterns to match the new sequence therefore looks like a reasonable adjustment. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sched_reorder): Remove dead return after the early-return guard. gcc/testsuite/ChangeLog: PR target/111037 PR target/113248 * gcc.target/riscv/rvv/vsetvl/pr111037-1.c: Update vsetvl patterns to match post-reorder asm sequence. * gcc.target/riscv/rvv/vsetvl/pr111037-4.c: Likewise. * gcc.target/riscv/rvv/vsetvl/pr113248.c: Likewise. Diff: --- gcc/config/riscv/riscv.cc | 1 - gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c | 4 ++-- 4 files changed, 6 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index a2730a90ca8b..9ab4ab3cd1d9 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -11413,7 +11413,6 @@ riscv_sched_reorder (FILE *, int, rtx_insn **ready, int *nreadyp, int) if (!last_vconfig.valid || *nreadyp == 1) return riscv_issue_rate (); - return riscv_issue_rate (); int nready = *nreadyp; int priority = INSN_PRIORITY (ready[nready - 1]); for (int i = nready - 1; i >= 0; i--) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c index 803ce5702ebf..e346e64f4939 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c @@ -11,5 +11,5 @@ void foo(_Float16 y, int64_t *i64p) asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy)); } -/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e16,\s*m1,\s*t[au],\s*m[au]} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c index 5949085bdc9f..6cf3c64679f1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c @@ -12,5 +12,5 @@ void foo(_Float16 y, int16_t z, int64_t *i64p) asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy), "vr" (vz)); } -/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e16,\s*m1,\s*t[au],\s*m[au]} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c index d95281362a83..fe5739339779 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c @@ -11,5 +11,5 @@ void foo(_Float16 y, int64_t *i64p) asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy)); } -/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e16,\s*m1,\s*t[au],\s*m[au]} 1 } } */
