https://gcc.gnu.org/g:788ae3f0c1e0b7e11dc9931066639c7036161776
commit r17-1466-g788ae3f0c1e0b7e11dc9931066639c7036161776 Author: tobby.li <[email protected]> Date: Wed May 20 17:21:44 2026 +0800 arm: support star-mc3 CPU This patch adds the -mcpu support for the ArmChina star-mc3 CPU which is an ARMv8.1-M Mainline CPU supporting MVE and PACBTI by default. -mcpu=star-mc3 switch by default matches to -march=armv8.1-m.main+pacbti+mve.fp+fp.dp. The cde feature is supported by specifying +cdecpN (e.g. -mcpu=star-mc3+cdecp<N>), where N is the coprocessor number in the range 0 to 7. Also following options are provided to disable default features. +nomve.fp (disables MVE Floating point) +nomve (disables MVE Integer and MVE Floating point) +nodsp (disables dsp, MVE Integer and MVE Floating point) +nopacbti (disables pacbti) +nofp (disables floating point and MVE floating point) Signed-off-by: LangXing Li <[email protected]> gcc/ChangeLog: * config/arm/arm-cpus.in (star-mc3): New CPU. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * doc/invoke.texi: Update docs. Diff: --- gcc/config/arm/arm-cpus.in | 21 +++++++++++++++++++++ gcc/config/arm/arm-tables.opt | 3 +++ gcc/config/arm/arm-tune.md | 3 ++- gcc/doc/invoke.texi | 19 ++++++++++--------- 4 files changed, 36 insertions(+), 10 deletions(-) diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index db674b85af1f..16b68fc7c2fc 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1685,6 +1685,27 @@ begin cpu star-mc1 costs v7m end cpu star-mc1 +begin cpu star-mc3 + cname starmc3 + tune flags LDSCHED + architecture armv8.1-m.main+pacbti+mve.fp+fp.dp + option nopacbti remove pacbti + option nomve.fp remove mve_float + option nomve remove mve mve_float + option nofp remove ALL_FP mve_float + option nodsp remove MVE mve_float + option cdecp0 add cdecp0 + option cdecp1 add cdecp1 + option cdecp2 add cdecp2 + option cdecp3 add cdecp3 + option cdecp4 add cdecp4 + option cdecp5 add cdecp5 + option cdecp6 add cdecp6 + option cdecp7 add cdecp7 + isa quirk_no_asmcpu + costs v7m +end cpu star-mc3 + begin cpu cortex-m85 cname cortexm85 tune flags LDSCHED diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 8183d9f3a5cd..0e2ddbe23a19 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -285,6 +285,9 @@ Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55) EnumValue Enum(processor_type) String(star-mc1) Value( TARGET_CPU_starmc1) +EnumValue +Enum(processor_type) String(star-mc3) Value( TARGET_CPU_starmc3) + EnumValue Enum(processor_type) String(cortex-m85) Value( TARGET_CPU_cortexm85) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index ddf1a2d0d4f5..dab67f185df1 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -50,5 +50,6 @@ cortexa76cortexa55,neoversev1,neoversen2, cortexm23,cortexm33,cortexm35p, cortexm52,cortexm55,starmc1, - cortexm85,cortexr52,cortexr52plus" + starmc3,cortexm85,cortexr52, + cortexr52plus" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9a753749870c..186ed95db949 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -23732,7 +23732,7 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t}, @samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{star-mc1}, -@samp{xgene1}. +@samp{star-mc3}, @samp{xgene1}. Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: @@ -23792,28 +23792,29 @@ The following extension options are common to the listed CPUs: @table @samp @item +nodsp Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}, -@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. +@samp{cortex-m52}, @samp{cortex-m55}, @samp{cortex-m85} and @samp{star-mc3}. Also disable the M-Profile Vector Extension (MVE) integer and single precision floating-point instructions on -@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. +@samp{cortex-m52}, @samp{cortex-m55}, @samp{cortex-m85} and @samp{star-mc3}. @item +nopacbti Disable the Pointer Authentication and Branch Target Identification Extension -on @samp{cortex-m52} and @samp{cortex-m85}. +on @samp{cortex-m52}, @samp{cortex-m85} and @samp{star-mc3}. @item +nomve Disable the M-Profile Vector Extension (MVE) integer and single precision -floating-point instructions on @samp{cortex-m52}, @samp{cortex-m55} and -@samp{cortex-m85}. +floating-point instructions on @samp{cortex-m52}, @samp{cortex-m55}, +@samp{cortex-m85} and @samp{star-mc3}. @item +nomve.fp Disable the M-Profile Vector Extension (MVE) single precision floating-point -instructions on @samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. +instructions on @samp{cortex-m52}, @samp{cortex-m55}, @samp{cortex-m85} and +@samp{star-mc3}. @item +cdecp0, +cdecp1, ... , +cdecp7 Enable the Custom Datapath Extension (CDE) on selected coprocessors according to the numbers given in the options in the range 0 to 7 on @samp{cortex-m52}, -@samp{cortex-m55}, @samp{cortex-m85} and @samp{star-mc1}. +@samp{cortex-m55}, @samp{cortex-m85}, @samp{star-mc1} and @samp{star-mc3}. @item +nofp Disables the floating-point instructions on @samp{arm9e}, @@ -23821,7 +23822,7 @@ Disables the floating-point instructions on @samp{arm9e}, @samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s}, @samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p}, -@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. +@samp{cortex-m52}, @samp{cortex-m55}, @samp{cortex-m85} and @samp{star-mc3}. Disables the floating-point and SIMD instructions on @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
