https://gcc.gnu.org/g:6457645578484efeec67df67bfa7317c70e0a5d7
commit 6457645578484efeec67df67bfa7317c70e0a5d7 Author: Alexandre Oliva <[email protected]> Date: Wed Jun 24 10:47:27 2026 -0300 testsuite: riscv: add riscv_v_okc Diff: --- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c | 2 +- gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 2 +- gcc/testsuite/gcc.dg/vect/pr88598-1.c | 2 +- gcc/testsuite/gcc.dg/vect/pr88598-2.c | 2 +- gcc/testsuite/gcc.dg/vect/pr88598-3.c | 2 +- gcc/testsuite/gcc.dg/vect/slp-26.c | 8 +- gcc/testsuite/gcc.dg/vect/slp-reduc-4.c | 2 +- gcc/testsuite/gcc.dg/vect/slp-reduc-7.c | 4 +- gcc/testsuite/gcc.dg/vect/slp-reduc-sad-2.c | 2 +- gcc/testsuite/gcc.dg/vect/tsvc/tsvc.h | 2 +- gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s1115.c | 4 +- gcc/testsuite/gcc.dg/vect/vect-93.c | 4 +- .../gcc.dg/vect/vect-early-break_133_pfa3.c | 2 +- .../gcc.dg/vect/vect-early-break_133_pfa4.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-early-break_39.c | 4 +- gcc/testsuite/gcc.dg/vect/vect-early-break_56.c | 2 + gcc/testsuite/gcc.dg/vect/vect-early-break_57.c | 4 +- gcc/testsuite/gcc.dg/vect/vect-early-break_63.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-early-break_81.c | 4 +- gcc/testsuite/gcc.dg/vect/vect-reduc-chain-1.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-reduc-chain-2.c | 6 +- gcc/testsuite/gcc.dg/vect/vect-reduc-chain-3.c | 4 +- .../gcc.dg/vect/vect-reduc-chain-dot-slp-1.c | 2 +- .../gcc.dg/vect/vect-reduc-chain-dot-slp-2.c | 2 +- .../gcc.dg/vect/vect-reduc-chain-dot-slp-3.c | 2 +- .../gcc.dg/vect/vect-reduc-chain-dot-slp-4.c | 2 +- .../rvv/autovec/vls-vlmax/shuffle-interleave-run.c | 2 +- gcc/testsuite/lib/target-supports.exp | 135 ++++++++++++--------- 28 files changed, 121 insertions(+), 92 deletions(-) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c index c2e5dfea35fb..ab88feed3d91 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c @@ -13,4 +13,4 @@ float summul(int n, float *arg1, float *arg2) return res1; } -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_masked_load } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_masked_load xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c index f63b42a271af..20e5baa19272 100644 --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c @@ -23,4 +23,4 @@ void foo(unsigned *p1, unsigned short *p2) get an unrolled epilogue loop. Also disable for AArch64 Advanced SIMD, because there we can vectorize the epilogue using mixed vector sizes. Likewise for AMD GCN and RVV. */ -/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { ! amdgcn*-*-* } && { ! riscv_v } } } } } } */ +/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { ! amdgcn*-*-* } && { ! riscv_v_okc } } } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr88598-1.c b/gcc/testsuite/gcc.dg/vect/pr88598-1.c index d4a0014f543d..7320a12a0ef0 100644 --- a/gcc/testsuite/gcc.dg/vect/pr88598-1.c +++ b/gcc/testsuite/gcc.dg/vect/pr88598-1.c @@ -51,4 +51,4 @@ main () /* ??? We need more constant folding for this to work with fully-masked loops. */ -/* { dg-final { scan-tree-dump-not {REDUC_PLUS} "optimized" { xfail { aarch64_sve || riscv_v } } } } */ +/* { dg-final { scan-tree-dump-not {REDUC_PLUS} "optimized" { xfail { aarch64_sve || riscv_v_okc } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr88598-2.c b/gcc/testsuite/gcc.dg/vect/pr88598-2.c index 57d0c885bec3..22a7fd2d5c9c 100644 --- a/gcc/testsuite/gcc.dg/vect/pr88598-2.c +++ b/gcc/testsuite/gcc.dg/vect/pr88598-2.c @@ -51,4 +51,4 @@ main () /* ??? We need more constant folding for this to work with fully-masked loops. */ -/* { dg-final { scan-tree-dump-not {REDUC_PLUS} "optimized" { xfail { aarch64_sve || riscv_v } } } } */ +/* { dg-final { scan-tree-dump-not {REDUC_PLUS} "optimized" { xfail { aarch64_sve || riscv_v_okc } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr88598-3.c b/gcc/testsuite/gcc.dg/vect/pr88598-3.c index ee3a9effd8de..556daa5b1ace 100644 --- a/gcc/testsuite/gcc.dg/vect/pr88598-3.c +++ b/gcc/testsuite/gcc.dg/vect/pr88598-3.c @@ -51,4 +51,4 @@ main () /* ??? We need more constant folding for this to work with fully-masked loops. */ -/* { dg-final { scan-tree-dump-not {REDUC_PLUS} "optimized" { xfail { aarch64_sve || riscv_v } } } } */ +/* { dg-final { scan-tree-dump-not {REDUC_PLUS} "optimized" { xfail { aarch64_sve || riscv_v_okc } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/slp-26.c b/gcc/testsuite/gcc.dg/vect/slp-26.c index b916bb3ff9ce..f7fb1b650596 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-26.c +++ b/gcc/testsuite/gcc.dg/vect/slp-26.c @@ -47,8 +47,8 @@ int main (void) return 0; } -/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { mips_msa || { amdgcn-*-* || { riscv_v || loongarch_sx } } } } } } } */ -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { mips_msa || { amdgcn-*-* || { riscv_v || loongarch_sx } } } } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { mips_msa || { amdgcn-*-* || { riscv_v || loongarch_sx } } } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { mips_msa || { amdgcn-*-* || { riscv_v_okc || loongarch_sx } } } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { mips_msa || { amdgcn-*-* || { riscv_v_okc || loongarch_sx } } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { mips_msa || { amdgcn-*-* || { riscv_v_okc || loongarch_sx } } } } } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { mips_msa } } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { loongarch_sx || { riscv_v || amdgcn-*-* } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { loongarch_sx || { riscv_v_okc || amdgcn-*-* } } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc-4.c b/gcc/testsuite/gcc.dg/vect/slp-reduc-4.c index 23c1a7373d77..c02f27f79e87 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-reduc-4.c +++ b/gcc/testsuite/gcc.dg/vect/slp-reduc-4.c @@ -61,5 +61,5 @@ int main (void) reduction exceeds the number of elements in a 128-bit granule. */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! vect_multiple_sizes } xfail { vect_no_int_min_max || { aarch64_sve && vect_variable_length } } } } } */ /* { dg-final { scan-tree-dump "vectorizing stmts using SLP" "vect" { target { vect_multiple_sizes && { ! { vect_load_lanes && vect_strided8 } } } } } } */ -/* { dg-final { scan-tree-dump-times "VEC_PERM_EXPR" 0 "vect" { xfail { { aarch64_sve && vect_variable_length } || vect_no_int_min_max } } } } */ +/* { dg-final { scan-tree-dump-times "VEC_PERM_EXPR" 0 "vect" { xfail { { { aarch64_sve || riscv_v_okc } && vect_variable_length } || vect_no_int_min_max } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc-7.c b/gcc/testsuite/gcc.dg/vect/slp-reduc-7.c index 1e0de894cecd..da8e205ae6fb 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-reduc-7.c +++ b/gcc/testsuite/gcc.dg/vect/slp-reduc-7.c @@ -58,5 +58,5 @@ int main (void) /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail vect_no_int_add } } } */ /* For variable-length SVE, the number of scalar statements in the reduction exceeds the number of elements in a 128-bit granule. */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_no_int_add || { { aarch64_sve && vect_variable_length } || { riscv_v && vect_variable_length } } } } } } */ -/* { dg-final { scan-tree-dump-times "VEC_PERM_EXPR" 0 "vect" { xfail { aarch64_sve && vect_variable_length } } } } */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_no_int_add || { { aarch64_sve && vect_variable_length } || { riscv_v_okc && vect_variable_length } } } } } } */ +/* { dg-final { scan-tree-dump-times "VEC_PERM_EXPR" 0 "vect" { xfail { { aarch64_sve || riscv_v_okc } && vect_variable_length } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc-sad-2.c b/gcc/testsuite/gcc.dg/vect/slp-reduc-sad-2.c index 7d9255e48f21..6d6753000a95 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-reduc-sad-2.c +++ b/gcc/testsuite/gcc.dg/vect/slp-reduc-sad-2.c @@ -27,5 +27,5 @@ int x264_pixel_sad_8x8( uint8_t *pix1, uint8_t *pix2, int i_stride_pix2 ) /* { dg-final { scan-tree-dump "vect_recog_sad_pattern: detected" "vect" } } */ /* { dg-final { scan-tree-dump "vectorizing stmts using SLP" "vect" } } */ -/* { dg-final { scan-tree-dump-not "access with gaps requires scalar epilogue loop" "vect" } } */ +/* { dg-final { scan-tree-dump-not "access with gaps requires scalar epilogue loop" "vect" { xfail riscv_v_okc } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/tsvc/tsvc.h b/gcc/testsuite/gcc.dg/vect/tsvc/tsvc.h index 4d295d1ec296..1a454758efd4 100644 --- a/gcc/testsuite/gcc.dg/vect/tsvc/tsvc.h +++ b/gcc/testsuite/gcc.dg/vect/tsvc/tsvc.h @@ -1412,7 +1412,7 @@ real_t get_expected_result(const char * name) } else if (!strcmp (name, "s1113")) { return 51.947979f; } else if (!strcmp (name, "s1115")) { - return 1567.842896f; + return 1622.754150f; } else if (!strcmp (name, "s1119")) { return 1567.842896f; } else if (!strcmp (name, "s111")) { diff --git a/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s1115.c b/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s1115.c index 3eda9940e68a..eb55467a62c6 100644 --- a/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s1115.c +++ b/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s1115.c @@ -13,7 +13,7 @@ real_t s1115(struct args_t * func_args) initialise_arrays(__func__); - for (int nl = 0; nl < 100*(iterations/LEN_2D); nl++) { + for (int nl = 0; nl < 100*iterations/LEN_2D; nl++) { for (int i = 0; i < LEN_2D; i++) { for (int j = 0; j < LEN_2D; j++) { aa[i][j] = aa[i][j]*cc[j][i] + bb[i][j]; @@ -38,4 +38,4 @@ int main (int argc, char **argv) return 0; } -/* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" { xfail { { ! aarch64_sve } && { ! riscv_v } } } } } */ +/* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" { xfail { { ! aarch64_sve } && { ! riscv_v_okc } } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-93.c b/gcc/testsuite/gcc.dg/vect/vect-93.c index 75af52d64349..7cd8f462cbac 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-93.c +++ b/gcc/testsuite/gcc.dg/vect/vect-93.c @@ -81,10 +81,10 @@ int main (void) the second loop in main requires vectorization of misaligned load. */ /* main && main1 together: */ -/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 2 "vect" { target powerpc*-*-* i?86-*-* x86_64-*-* } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 2 "vect" { target powerpc*-*-* riscv*-*-* i?86-*-* x86_64-*-* } } } */ /* in main1: */ -/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target !powerpc*-*-* !i?86-*-* !x86_64-*-* } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { ! { powerpc*-*-* riscv*-*-* i?86-*-* x86_64-*-* } } } } } */ /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_no_align && { ! vect_hw_misalign } } } } } */ /* in main: */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_133_pfa3.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_133_pfa3.c index 374a051b945e..9e93ac9445dd 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-early-break_133_pfa3.c +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_133_pfa3.c @@ -17,4 +17,4 @@ char * find(int n, char c) /* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ /* { dg-final { scan-tree-dump "Alignment of access forced using peeling" "vect" } } */ -/* { dg-final { scan-tree-dump "force alignment of string" "vect" } } */ +/* { dg-final { scan-tree-dump "force alignment of string" "vect" { xfail { riscv*-*-* } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_133_pfa4.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_133_pfa4.c index 297fb7e9b9be..02ade8514277 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-early-break_133_pfa4.c +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_133_pfa4.c @@ -17,4 +17,4 @@ char * find(int n, char c) /* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ /* { dg-final { scan-tree-dump-not "Alignment of access forced using peeling" "vect" } } */ -/* { dg-final { scan-tree-dump "force alignment of string" "vect" } } */ +/* { dg-final { scan-tree-dump "force alignment of string" "vect" { xfail { riscv*-*-* } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_39.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_39.c index bc862ad20e68..cac6d3ddca7e 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-early-break_39.c +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_39.c @@ -24,5 +24,5 @@ unsigned test4(unsigned x, unsigned n) } /* AArch64 will scalarize the load and is able to vectorize it. */ -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 1 "vect" { target aarch64*-*-* } } } */ -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 0 "vect" { target { ! aarch64*-*-* } } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 1 "vect" { target aarch64*-*-* riscv*-*-* } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 0 "vect" { target { ! { aarch64*-*-* riscv*-*-* } } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_56.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_56.c index 76a1f9b3f55c..1bd2a61e6d97 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-early-break_56.c +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_56.c @@ -45,6 +45,7 @@ int main1 () } /* check results: */ + #pragma GCC novector for (i = 0; i < n; i++) { if (sa[i+7] != sb[i] + sc[i] || ia[i+3] != ib[i] + ic[i]) @@ -80,6 +81,7 @@ int main2 () } /* check results: */ + #pragma GCC novector for (i = 0; i < n; i++) { if (sa[i+3] != sb[i] + sc[i] || ia[i+3] != ib[i] + ic[i]) diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_57.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_57.c index a4886654f152..31ed09da5c51 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-early-break_57.c +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_57.c @@ -6,8 +6,8 @@ /* { dg-additional-options "-Ofast" } */ /* Multiple loads of different alignments, we can't peel this. */ -/* { dg-final { scan-tree-dump-not "LOOP VECTORIZED" "vect" } } */ -/* { dg-final { scan-tree-dump-not "epilog loop required" "vect" } } */ +/* { dg-final { scan-tree-dump-not "LOOP VECTORIZED" "vect" { xfail { riscv*-*-* } } } } */ +/* { dg-final { scan-tree-dump-not "epilog loop required" "vect" { xfail { riscv*-*-* } } } } */ void abort (); diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_63.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_63.c index 1d9ff4ad6bac..3a8b5a053c8b 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-early-break_63.c +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_63.c @@ -26,4 +26,4 @@ liveloop (int start, int n, int *x, int *y) } /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ -/* { dg-final { scan-tree-dump-times "vec_stmt_relevant_p: stmt live but not relevant" 1 "vect" } } */ +/* { dg-final { scan-tree-dump "vec_stmt_relevant_p: stmt live but not relevant" "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_81.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_81.c index b58a4611d6b8..458910f69203 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-early-break_81.c +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_81.c @@ -6,8 +6,8 @@ /* { dg-additional-options "-Ofast" } */ /* Multiple loads with different misalignments. Can't peel need partial loop support. */ -/* { dg-final { scan-tree-dump-not "LOOP VECTORIZED" "vect" } } */ -/* { dg-final { scan-tree-dump-not "epilog loop required" "vect" } } */ +/* { dg-final { scan-tree-dump-not "LOOP VECTORIZED" "vect" { xfail { riscv*-*-* } } } } */ +/* { dg-final { scan-tree-dump-not "epilog loop required" "vect" { xfail { riscv*-*-* } } } } */ void abort (); unsigned short sa[32]; diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-1.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-1.c index 690307f6d554..92da53191b43 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-1.c +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-1.c @@ -61,4 +61,4 @@ main (void) } /* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "vect" } } */ -/* { dg-final { scan-tree-dump-times "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" 2 "vect" { target vect_sdot_qi } } } */ +/* { dg-final { scan-tree-dump-times "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" 2 "vect" { target vect_sdot_qi xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-2.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-2.c index 0d8d012ec2ea..a7cc8bfc4f74 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-2.c +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-2.c @@ -74,6 +74,6 @@ main (void) } /* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "vect" } } */ -/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target { vect_sdot_qi } } } } */ -/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target { vect_udot_qi } } } } */ -/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target { vect_sdot_hi } } } } */ +/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target { vect_sdot_qi } xfail riscv*-*-* } } } */ +/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target { vect_udot_qi } xfail riscv*-*-* } } } */ +/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target { vect_sdot_hi } xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-3.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-3.c index 1cefbe0b959f..cd39d35dc7a4 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-3.c +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-3.c @@ -64,5 +64,5 @@ main (void) __builtin_abort (); } -/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = SAD_EXPR" "vect" { target vect_udot_qi } } } */ -/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target vect_sdot_hi } } } */ +/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = SAD_EXPR" "vect" { target vect_udot_qi xfail riscv*-*-* } } } */ +/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target vect_sdot_hi xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-1.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-1.c index 0901357ea6ad..d3e389b575e3 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-1.c +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-1.c @@ -91,4 +91,4 @@ main (void) } /* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "vect" } } */ -/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target vect_sdot_qi } } } */ +/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target vect_sdot_qi xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-2.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-2.c index 818eeddcece1..354892c51f8e 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-2.c +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-2.c @@ -63,4 +63,4 @@ main (void) } /* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "vect" } } */ -/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target vect_sdot_qi } } } */ +/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target vect_sdot_qi xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-3.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-3.c index 87541cd83423..3a6a71757c78 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-3.c +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-3.c @@ -75,4 +75,4 @@ main (void) } /* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "vect" } } */ -/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target vect_sdot_hi } } } */ +/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target vect_sdot_hi xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-4.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-4.c index 11719430e582..1aca560d07a7 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-4.c +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-dot-slp-4.c @@ -59,4 +59,4 @@ main (void) } /* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "vect" } } */ -/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target vect_sdot_hi } } } */ +/* { dg-final { scan-tree-dump "vectorizing SLP node starting from: \\S+ = DOT_PROD_EXPR" "vect" { target vect_sdot_hi xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-run.c index 57748d95362f..a057dde8fb86 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-run.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do run } */ /* { dg-require-effective-target riscv_v_ok } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=m8 -std=gnu99" } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index c6ebbed4f4b5..109c24ced6b6 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -2348,6 +2348,25 @@ proc check_effective_target_riscv_b_ok { } { return 0 } +# Return 1 if we can compile code when using dg-add-options riscv_v + +proc check_effective_target_riscv_v_okc { } { + # If the target already supports v without any added options, + # we may assume we can compile just fine. + if { [check_effective_target_riscv_v] } { + return 1 + } + + # check if we can compile a testcase by adding 'v' to the arch + set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v] + if { [check_no_compiler_messages ${gcc_march}_compile assembly { + int main() { return 0; } } "-march=${gcc_march}"] } { + return 1 + } + + return 0 +} + # Return 1 if we can execute code when using dg-add-options riscv_v proc check_effective_target_riscv_v_ok { } { @@ -2527,7 +2546,7 @@ proc check_effective_target_riscv_v_misalign_ok { } { return 0 } - set gcc_march [riscv_get_arch] + set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v] if { [check_runtime ${gcc_march}_misalign_exec { int main() { unsigned char a[16] @@ -4679,7 +4698,7 @@ proc check_effective_target_vect_int { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] @@ -4711,7 +4730,7 @@ proc check_effective_target_vect_early_break { } { || [check_effective_target_arm_v8_neon_ok] || [check_effective_target_sse4] || [istarget amdgcn-*-*] - || [check_effective_target_riscv_v] + || [check_effective_target_riscv_v_okc] || [check_effective_target_loongarch_sx] }}] } @@ -4875,7 +4894,7 @@ proc check_effective_target_vect_intfloat_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -4898,7 +4917,7 @@ proc check_effective_target_vect_doubleint_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -4921,7 +4940,7 @@ proc check_effective_target_vect_intdouble_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -4955,7 +4974,7 @@ proc check_effective_target_vect_uintfloat_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -4975,7 +4994,7 @@ proc check_effective_target_vect_floatint_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -4993,7 +5012,7 @@ proc check_effective_target_vect_floatuint_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -5004,7 +5023,7 @@ proc check_effective_target_vect_floatuint_cvt { } { proc check_effective_target_vect_ext_char_longlong { } { return [check_cached_effective_target vect_ext_char_longlong { expr { ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -8410,7 +8429,7 @@ proc check_effective_target_vect_shift { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -8423,7 +8442,7 @@ proc check_effective_target_vect_var_shift { } { && [check_avx2_available]) || [istarget aarch64*-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] @@ -8442,7 +8461,7 @@ proc check_effective_target_whole_vector_shift { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) } { set answer 1 @@ -8475,7 +8494,7 @@ proc check_effective_target_vect_bool_cmp { } { || [istarget aarch64*-*-*] || [is-effective-target arm_neon] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -8498,7 +8517,7 @@ proc check_effective_target_vect_char_add { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] @@ -8516,7 +8535,7 @@ proc check_effective_target_vect_shift_char { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -8538,7 +8557,7 @@ proc check_effective_target_vect_long { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) } { set answer 1 @@ -8570,7 +8589,7 @@ proc check_effective_target_vect_float { } { && [check_effective_target_s390_vxe]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -8603,7 +8622,7 @@ proc check_effective_target_vect_double { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -8614,7 +8633,7 @@ proc check_effective_target_vect_double { } { proc check_effective_target_vect_double_cond_arith { } { return [expr { [check_effective_target_aarch64_sve] - || [check_effective_target_riscv_v] }] + || [check_effective_target_riscv_v_okc] }] } # Return 1 if the target supports hardware vectors of long long, 0 otherwise. @@ -8632,7 +8651,7 @@ proc check_effective_target_vect_long_long { } { && [check_effective_target_has_arch_pwr8]) || [istarget aarch64*-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) || [istarget amdgcn-*-*] }}] @@ -8690,7 +8709,7 @@ proc check_effective_target_vect_perm { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -8787,7 +8806,7 @@ proc check_effective_target_vect_perm_byte { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -8820,7 +8839,7 @@ proc check_effective_target_vect_perm_short { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -9042,7 +9061,7 @@ proc check_effective_target_vect_sdot_qi { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -9061,7 +9080,7 @@ proc check_effective_target_vect_udot_qi { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -9092,7 +9111,7 @@ proc check_effective_target_vect_sdot_hi { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -9108,7 +9127,7 @@ proc check_effective_target_vect_udot_hi { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -9126,7 +9145,7 @@ proc check_effective_target_vect_usad_char { } { || ([istarget powerpc*-*-*] && [check_p9vector_hw_available]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -9138,7 +9157,7 @@ proc check_effective_target_vect_avg_qi {} { return [expr { ([istarget aarch64*-*-*] && ![check_effective_target_aarch64_sve1_only]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }] } @@ -9179,7 +9198,7 @@ proc check_effective_target_vect_pack_trunc { } { && [check_effective_target_s390_vx]) || [istarget amdgcn*-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -9203,7 +9222,7 @@ proc check_effective_target_vect_unpack { } { && [check_effective_target_s390_vx]) || [istarget amdgcn*-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -9358,7 +9377,7 @@ proc check_effective_target_vect_check_ptrs { } { proc check_effective_target_vect_fully_masked { } { return [expr { [check_effective_target_aarch64_sve] || [istarget amdgcn*-*-*] - || [check_effective_target_riscv_v] }] + || [check_effective_target_riscv_v_okc] }] } # Return true if the target supports the @code{len_load} and @@ -9367,7 +9386,7 @@ proc check_effective_target_vect_fully_masked { } { proc check_effective_target_vect_len_load_store { } { return [expr { [check_effective_target_has_arch_pwr9] || [check_effective_target_s390_vx] - || [check_effective_target_riscv_v] }] + || [check_effective_target_riscv_v_okc] }] } # Return the value of parameter vect-partial-vector-usage specified for @@ -9430,7 +9449,7 @@ proc check_effective_target_vect_partial_vectors { } { proc check_effective_target_vect_element_align_preferred { } { return [expr { ([check_effective_target_aarch64_sve] && [check_effective_target_vect_variable_length]) - || [check_effective_target_riscv_v] }] + || [check_effective_target_riscv_v_okc] }] } # Return true if vectorization of v2qi/v4qi/v8qi/v16qi/v2hi store is enabed. @@ -9844,7 +9863,7 @@ proc check_effective_target_vect_masked_load { } { return [expr { [check_avx_available] || [check_effective_target_aarch64_sve] || [istarget amdgcn*-*-*] - || [check_effective_target_riscv_v] } ] + || [check_effective_target_riscv_v_okc] } ] } # Return 1 if the target supports vector masked stores. @@ -9853,7 +9872,7 @@ proc check_effective_target_vect_masked_store { } { return [expr { [check_avx_available] || [check_effective_target_aarch64_sve] || [istarget amdgcn*-*-*] - || [check_effective_target_riscv_v] }] + || [check_effective_target_riscv_v_okc] }] } # Return 1 if the target supports vector gather loads via internal functions. @@ -9861,7 +9880,7 @@ proc check_effective_target_vect_masked_store { } { proc check_effective_target_vect_gather_load_ifn { } { return [expr { [check_effective_target_aarch64_sve] || [istarget amdgcn*-*-*] - || [check_effective_target_riscv_v] }] + || [check_effective_target_riscv_v_okc] }] } # Return 1 if the target supports vector scatter stores. @@ -9869,7 +9888,7 @@ proc check_effective_target_vect_gather_load_ifn { } { proc check_effective_target_vect_scatter_store { } { return [expr { [check_effective_target_aarch64_sve] || [istarget amdgcn*-*-*] - || [check_effective_target_riscv_v] + || [check_effective_target_riscv_v_okc] || [check_effective_target_loongarch_sx] }] } @@ -9888,7 +9907,7 @@ proc check_effective_target_vect_condition { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -9908,7 +9927,7 @@ proc check_effective_target_vect_cond_mixed { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -9928,7 +9947,7 @@ proc check_effective_target_vect_char_mult { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -9949,7 +9968,7 @@ proc check_effective_target_vect_short_mult { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -9969,7 +9988,7 @@ proc check_effective_target_vect_int_mult { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -9993,7 +10012,7 @@ proc check_effective_target_vect_long_mult { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) || [istarget amdgcn-*-*] } { @@ -10021,7 +10040,7 @@ proc check_effective_target_vect_extract_even_odd { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -10041,7 +10060,7 @@ proc check_effective_target_vect_interleave { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -10099,7 +10118,7 @@ proc available_vector_sizes { } { # 6 different lane counts, and 4 element sizes lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2 } elseif { [istarget riscv*-*-*] } { - if { [check_effective_target_riscv_v] } { + if { [check_effective_target_riscv_v_okc] } { lappend result 0 32 64 128 } lappend result 128 @@ -10167,7 +10186,7 @@ proc check_effective_target_vect_call_copysignf { } { || [istarget aarch64*-*-*] || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -10208,7 +10227,7 @@ proc check_effective_target_vect_call_sqrtf { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) + && [check_effective_target_riscv_v_okc]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) }}] } @@ -10323,7 +10342,7 @@ proc check_effective_target_vect_call_roundf { } { proc check_effective_target_vect_logical_reduc { } { return [expr { [check_effective_target_aarch64_sve] || [istarget amdgcn-*-*] - || [check_effective_target_riscv_v] + || [check_effective_target_riscv_v_okc] || [check_effective_target_loongarch_sx] || [check_effective_target_x86] || [check_effective_target_s390_vx]}] @@ -10334,7 +10353,7 @@ proc check_effective_target_vect_logical_reduc { } { proc check_effective_target_vect_fold_extract_last { } { return [expr { [check_effective_target_aarch64_sve] || [istarget amdgcn*-*-*] - || [check_effective_target_riscv_v] }] + || [check_effective_target_riscv_v_okc] }] } # Return 1 if the target supports section-anchors @@ -11267,7 +11286,7 @@ proc check_effective_target_vect_sizes_16B_8B { } { if { [check_avx_available] || [is-effective-target arm_neon] || [istarget aarch64*-*-*] - || [check_effective_target_riscv_v] } { + || [check_effective_target_riscv_v_okc] } { return 1; } else { return 0; @@ -12787,10 +12806,18 @@ proc check_vect_support_and_set_flags { } { lappend DEFAULT_VECTCFLAGS "-mno-vector-strict-align" } } elseif [check_effective_target_riscv_v_ok] { + set dg-do-what-default run foreach item [add_options_for_riscv_v ""] { lappend DEFAULT_VECTCFLAGS $item } + if [check_effective_target_riscv_v_misalign_ok] { + lappend DEFAULT_VECTCFLAGS "-mno-vector-strict-align" + } + } elseif [check_effective_target_riscv_v_okc] { set dg-do-what-default compile + foreach item [add_options_for_riscv_v ""] { + lappend DEFAULT_VECTCFLAGS $item + } } else { # Current architecture cannot support vectors (e.g. the # dependent D extension is missing). @@ -13484,7 +13511,7 @@ proc check_effective_target_builtin_eh_return { } { proc check_effective_target_vect_max_reduc { } { if { [istarget aarch64*-*-*] || [is-effective-target arm_neon] - || [check_effective_target_riscv_v] + || [check_effective_target_riscv_v_okc] || [check_effective_target_loongarch_sx] } { return 1 }
