https://gcc.gnu.org/g:845ea1c038a80d6f8052242d31b4eb62ec56a6b2
commit r17-1973-g845ea1c038a80d6f8052242d31b4eb62ec56a6b2 Author: Abhishek Kaushik <[email protected]> Date: Fri Jun 26 13:09:16 2026 +0000 aarch64: Add SVE2 unpredicated SMULH/UMULH patterns SVE has predicated SMULH and UMULH, while SVE2 provides unpredicated forms. The ACLE _x forms carry an inactive predicate wrapper in RTL, so add a split that removes the UNSPEC_PRED_X wrapper from MUL_HIGHPART and add a pattern that emits the corresponding unpredicated form. Add ACLE asm tests for all signed and unsigned integer element widths, covering vector, scalar and immediate operands. Bootstrapped and regression tested on aarch64-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64-sve2.md: Add unpredicated high-part multiplication section. (@aarch64_sve2_<optab><mode>): New insn. * config/aarch64/aarch64-sve.md (@aarch64_pred_<optab><mode>): Change to define_insn_and_split and split SVE2 highpart multiplication into unpredicated MUL_HIGHPART. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve2/acle/asm/mulh_s8.c: New test. * gcc.target/aarch64/sve2/acle/asm/mulh_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/mulh_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/mulh_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/mulh_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/mulh_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/mulh_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/mulh_u64.c: Likewise. Diff: --- gcc/config/aarch64/aarch64-sve.md | 9 ++- gcc/config/aarch64/aarch64-sve2.md | 17 ++++++ .../gcc.target/aarch64/sve2/acle/asm/mulh_s16.c | 70 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/mulh_s32.c | 70 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/mulh_s64.c | 70 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/mulh_s8.c | 70 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/mulh_u16.c | 70 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/mulh_u32.c | 70 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/mulh_u64.c | 70 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/mulh_u8.c | 70 ++++++++++++++++++++++ 10 files changed, 585 insertions(+), 1 deletion(-) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 67947b62e84f..105b34eb8fa9 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -4897,7 +4897,7 @@ ) ;; Predicated highpart multiplication. -(define_insn "@aarch64_pred_<optab><mode>" +(define_insn_and_split "@aarch64_pred_<optab><mode>" [(set (match_operand:SVE_I 0 "register_operand") (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand") @@ -4911,6 +4911,13 @@ [ w , Upl , 0 , w ; * ] <su>mulh\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype> [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;<su>mulh\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype> } + "TARGET_SVE2" + [(set (match_dup 0) + (unspec:SVE_I + [(match_dup 2) + (match_dup 3)] + MUL_HIGHPART))] + "" [(set_attr "sve_type" "sve_int_mul")] ) diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 1d428619c075..90a0402d0176 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -56,6 +56,7 @@ ;; ---- [INT] Multi-register operations ;; ---- [INT] Clamp to minimum/maximum ;; ---- [INT] Multiplication +;; ---- [INT] Unpredicated high-part multiplication ;; ---- [INT] Scaled high-part multiplication ;; ---- [INT] General binary arithmetic that maps to unspecs ;; ---- [INT] Saturating binary arithmetic @@ -977,6 +978,22 @@ [(set_attr "sve_type" "sve_int_mul")] ) +;; ------------------------------------------------------------------------- +;; ---- [INT] Unpredicated high-part multiplication +;; ------------------------------------------------------------------------- + +;; SVE2 unpredicated SMULH/UMULH. +(define_insn "@aarch64_sve2_<optab><mode>" + [(set (match_operand:SVE_I 0 "register_operand" "=w") + (unspec:SVE_I + [(match_operand:SVE_I 1 "register_operand" "w") + (match_operand:SVE_I 2 "register_operand" "w")] + MUL_HIGHPART))] + "TARGET_SVE2" + "<su>mulh\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>" + [(set_attr "sve_type" "sve_int_mul")] +) + ;; ------------------------------------------------------------------------- ;; ---- [INT] Scaled high-part multiplication ;; ------------------------------------------------------------------------- diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_s16.c new file mode 100644 index 000000000000..c536e736d25d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_s16.c @@ -0,0 +1,70 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_s16_x_tied1: +** smulh z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_s16_x_tied1, svint16_t, + z0 = svmulh_s16_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_s16_x_tied2: +** smulh z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_s16_x_tied2, svint16_t, + z0 = svmulh_s16_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_s16_x_untied: +** smulh z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_s16_x_untied, svint16_t, + z0 = svmulh_s16_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** smulh z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svmulh_n_s16_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_w0_s16_x_untied: +** mov z0\.h, w0 +** smulh z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s16_x_untied, svint16_t, int16_t, + z0 = svmulh_n_s16_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_s16_x_tied1: +** mov (z[0-9]+\.h), #11 +** smulh z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s16_x_tied1, svint16_t, + z0 = svmulh_n_s16_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_s16_x_untied: +** mov z0\.h, #11 +** smulh z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s16_x_untied, svint16_t, + z0 = svmulh_n_s16_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_s32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_s32.c new file mode 100644 index 000000000000..93c8d1829d3f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_s32.c @@ -0,0 +1,70 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_s32_x_tied1: +** smulh z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_s32_x_tied1, svint32_t, + z0 = svmulh_s32_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_s32_x_tied2: +** smulh z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_s32_x_tied2, svint32_t, + z0 = svmulh_s32_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_s32_x_untied: +** smulh z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_s32_x_untied, svint32_t, + z0 = svmulh_s32_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** smulh z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svmulh_n_s32_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_w0_s32_x_untied: +** mov z0\.s, w0 +** smulh z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s32_x_untied, svint32_t, int32_t, + z0 = svmulh_n_s32_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_s32_x_tied1: +** mov (z[0-9]+\.s), #11 +** smulh z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s32_x_tied1, svint32_t, + z0 = svmulh_n_s32_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_s32_x_untied: +** mov z0\.s, #11 +** smulh z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s32_x_untied, svint32_t, + z0 = svmulh_n_s32_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_s64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_s64.c new file mode 100644 index 000000000000..de30a4cdc2ae --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_s64.c @@ -0,0 +1,70 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_s64_x_tied1: +** smulh z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_s64_x_tied1, svint64_t, + z0 = svmulh_s64_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_s64_x_tied2: +** smulh z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_s64_x_tied2, svint64_t, + z0 = svmulh_s64_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_s64_x_untied: +** smulh z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_s64_x_untied, svint64_t, + z0 = svmulh_s64_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** smulh z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svmulh_n_s64_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_x0_s64_x_untied: +** mov z0\.d, x0 +** smulh z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_s64_x_untied, svint64_t, int64_t, + z0 = svmulh_n_s64_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_s64_x_tied1: +** mov (z[0-9]+\.d), #11 +** smulh z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s64_x_tied1, svint64_t, + z0 = svmulh_n_s64_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_s64_x_untied: +** mov z0\.d, #11 +** smulh z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s64_x_untied, svint64_t, + z0 = svmulh_n_s64_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_s8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_s8.c new file mode 100644 index 000000000000..4503951ccce4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_s8.c @@ -0,0 +1,70 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_s8_x_tied1: +** smulh z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_s8_x_tied1, svint8_t, + z0 = svmulh_s8_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_s8_x_tied2: +** smulh z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_s8_x_tied2, svint8_t, + z0 = svmulh_s8_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_s8_x_untied: +** smulh z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_s8_x_untied, svint8_t, + z0 = svmulh_s8_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** smulh z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svmulh_n_s8_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_w0_s8_x_untied: +** mov z0\.b, w0 +** smulh z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s8_x_untied, svint8_t, int8_t, + z0 = svmulh_n_s8_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_s8_x_tied1: +** mov (z[0-9]+\.b), #11 +** smulh z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s8_x_tied1, svint8_t, + z0 = svmulh_n_s8_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_s8_x_untied: +** mov z0\.b, #11 +** smulh z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s8_x_untied, svint8_t, + z0 = svmulh_n_s8_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_u16.c new file mode 100644 index 000000000000..e5e3a00311c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_u16.c @@ -0,0 +1,70 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_u16_x_tied1: +** umulh z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_u16_x_tied1, svuint16_t, + z0 = svmulh_u16_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_u16_x_tied2: +** umulh z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_u16_x_tied2, svuint16_t, + z0 = svmulh_u16_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_u16_x_untied: +** umulh z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_u16_x_untied, svuint16_t, + z0 = svmulh_u16_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** umulh z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svmulh_n_u16_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_w0_u16_x_untied: +** mov z0\.h, w0 +** umulh z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svmulh_n_u16_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_u16_x_tied1: +** mov (z[0-9]+\.h), #11 +** umulh z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u16_x_tied1, svuint16_t, + z0 = svmulh_n_u16_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_u16_x_untied: +** mov z0\.h, #11 +** umulh z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u16_x_untied, svuint16_t, + z0 = svmulh_n_u16_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_u32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_u32.c new file mode 100644 index 000000000000..dfa037f4ac1b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_u32.c @@ -0,0 +1,70 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_u32_x_tied1: +** umulh z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_u32_x_tied1, svuint32_t, + z0 = svmulh_u32_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_u32_x_tied2: +** umulh z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_u32_x_tied2, svuint32_t, + z0 = svmulh_u32_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_u32_x_untied: +** umulh z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_u32_x_untied, svuint32_t, + z0 = svmulh_u32_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** umulh z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svmulh_n_u32_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_w0_u32_x_untied: +** mov z0\.s, w0 +** umulh z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svmulh_n_u32_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_u32_x_tied1: +** mov (z[0-9]+\.s), #11 +** umulh z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u32_x_tied1, svuint32_t, + z0 = svmulh_n_u32_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_u32_x_untied: +** mov z0\.s, #11 +** umulh z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u32_x_untied, svuint32_t, + z0 = svmulh_n_u32_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_u64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_u64.c new file mode 100644 index 000000000000..03a2a9f455c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_u64.c @@ -0,0 +1,70 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_u64_x_tied1: +** umulh z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_u64_x_tied1, svuint64_t, + z0 = svmulh_u64_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_u64_x_tied2: +** umulh z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_u64_x_tied2, svuint64_t, + z0 = svmulh_u64_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_u64_x_untied: +** umulh z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_u64_x_untied, svuint64_t, + z0 = svmulh_u64_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** umulh z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svmulh_n_u64_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_x0_u64_x_untied: +** mov z0\.d, x0 +** umulh z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svmulh_n_u64_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_u64_x_tied1: +** mov (z[0-9]+\.d), #11 +** umulh z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u64_x_tied1, svuint64_t, + z0 = svmulh_n_u64_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_u64_x_untied: +** mov z0\.d, #11 +** umulh z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u64_x_untied, svuint64_t, + z0 = svmulh_n_u64_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_u8.c new file mode 100644 index 000000000000..c0bc7ee1e069 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mulh_u8.c @@ -0,0 +1,70 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_u8_x_tied1: +** umulh z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_u8_x_tied1, svuint8_t, + z0 = svmulh_u8_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_u8_x_tied2: +** umulh z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_u8_x_tied2, svuint8_t, + z0 = svmulh_u8_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_u8_x_untied: +** umulh z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_u8_x_untied, svuint8_t, + z0 = svmulh_u8_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** umulh z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svmulh_n_u8_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_w0_u8_x_untied: +** mov z0\.b, w0 +** umulh z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svmulh_n_u8_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_u8_x_tied1: +** mov (z[0-9]+\.b), #11 +** umulh z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u8_x_tied1, svuint8_t, + z0 = svmulh_n_u8_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_u8_x_untied: +** mov z0\.b, #11 +** umulh z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u8_x_untied, svuint8_t, + z0 = svmulh_n_u8_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11))
