https://gcc.gnu.org/g:e71bc0f8d7f93cff7129a867bc12b75048b1fab2
commit r17-2012-ge71bc0f8d7f93cff7129a867bc12b75048b1fab2 Author: Mark Zhuang <[email protected]> Date: Tue Jun 30 07:21:20 2026 -0600 [PATCH] RISC-V: Add basic Spacemit-A100 core support Add the Spacemit-A100 processor to -mcpu/-mtune. The A100 is an in-order, dual-issue core whose microarchitecture is close to the X60, so for now it reuses the Spacemit X60 costs. On the ISA side, the A100 is closest to the X100. The main differences are that it does not implement the H (hypervisor) extension, its vector length is VLEN=1024 (zvl1024b), and it has the xsmtvdotii extension. gcc/ChangeLog: * config/riscv/riscv-ext-spacemit.def (xsmtvdotii): New extension. * config/riscv/riscv-ext.opt: Regenerate. * config/riscv/riscv-cores.def (RISCV_TUNE): Add spacemit-a100. (RISCV_CORE): Add spacemit-a100. * doc/riscv-ext.texi: Regenerate. * doc/riscv-mcpu.texi: Regenerate. * doc/riscv-mtune.texi: Regenerate. gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-spacemit-a100.c: New test. Signed-off-by: Mark Zhuang <[email protected]> Diff: --- gcc/config/riscv/riscv-cores.def | 7 ++ gcc/config/riscv/riscv-ext-spacemit.def | 13 ++++ gcc/config/riscv/riscv-ext.opt | 3 + gcc/doc/riscv-ext.texi | 4 ++ gcc/doc/riscv-mcpu.texi | 4 +- gcc/doc/riscv-mtune.texi | 2 + .../gcc.target/riscv/mcpu-spacemit-a100.c | 80 ++++++++++++++++++++++ 7 files changed, 112 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 6ed9dad8be23..57c8e76b2bd2 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -53,6 +53,7 @@ RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info) RISCV_TUNE("xiangshan-kunminghu", xiangshan, generic_ooo_tune_info) RISCV_TUNE("spacemit-x60", spacemit_x60, spacemit_x60_tune_info) RISCV_TUNE("spacemit-x100", generic_ooo, spacemit_x100_tune_info) +RISCV_TUNE("spacemit-a100", spacemit_x60, spacemit_x60_tune_info) RISCV_TUNE("arc-v-rhx-100-series", arcv_rhx100, arcv_rhx100_tune_info) RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info) RISCV_TUNE("size", generic, optimize_size_tune_info) @@ -227,5 +228,11 @@ RISCV_CORE("spacemit-x100", "rva23s64_smepmp_smnpm_smstateen_sspm_zbc_zbkc_" "zvksc_zvksg_zvl256b_xsmtvdot", "spacemit-x100") +RISCV_CORE("spacemit-a100", "rva23u64_zfh_zbc_zbkc_zfbfmin_smepmp_smnpm_" + "smstateen_sscofpmf_ssnpm_sspm_ssstateen_sstc_svinval_" + "svnapot_svpbmt_zifencei_zvfh_zvfbfwma_zvkng_zvknha_" + "zvknc_zvksc_zvksg_zvl1024b_xsmtvdotii", + "spacemit-a100") + #undef RISCV_CORE #undef RISCV_CORE_ALIAS diff --git a/gcc/config/riscv/riscv-ext-spacemit.def b/gcc/config/riscv/riscv-ext-spacemit.def index e9ba547d7450..681c2c156c89 100644 --- a/gcc/config/riscv/riscv-ext-spacemit.def +++ b/gcc/config/riscv/riscv-ext-spacemit.def @@ -34,3 +34,16 @@ DEFINE_RISCV_EXT( /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, /* EXTRA_EXTENSION_FLAGS */ 0) +DEFINE_RISCV_EXT( + /* NAME */ xsmtvdotii, + /* UPPERCASE_NAME */ XSMTVDOTII, + /* FULL_NAME */ "SpacemiT vector dot product II extension", + /* DESC */ "", + /* URL */ "https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md";, + /* DEP_EXTS */ ({"xsmtvdot"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xsmt, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt index 875a8626a648..843b95fc35be 100644 --- a/gcc/config/riscv/riscv-ext.opt +++ b/gcc/config/riscv/riscv-ext.opt @@ -480,3 +480,6 @@ Mask(XANDESVPACKFPH) Var(riscv_xandes_subext) Mask(XANDESVDOT) Var(riscv_xandes_subext) Mask(XSMTVDOT) Var(riscv_xsmt_subext) + +Mask(XSMTVDOTII) Var(riscv_xsmt_subext) + diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi index 43c836fa77bd..41614790ab82 100644 --- a/gcc/doc/riscv-ext.texi +++ b/gcc/doc/riscv-ext.texi @@ -762,4 +762,8 @@ @tab 1.0 @tab SpacemiT vector dot product extension +@item @samp{xsmtvdotii} +@tab 1.0 +@tab SpacemiT vector dot product II extension + @end multitable diff --git a/gcc/doc/riscv-mcpu.texi b/gcc/doc/riscv-mcpu.texi index 9ccb265c3662..6e3c2adc2fb7 100644 --- a/gcc/doc/riscv-mcpu.texi +++ b/gcc/doc/riscv-mcpu.texi @@ -98,4 +98,6 @@ by particular CPU name. Permissible values for this option are: @samp{spacemit-x60}, -@samp{spacemit-x100}. +@samp{spacemit-x100}, + +@samp{spacemit-a100}. diff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi index d40ba7f7f15c..101d81d3709f 100644 --- a/gcc/doc/riscv-mtune.texi +++ b/gcc/doc/riscv-mtune.texi @@ -56,6 +56,8 @@ particular CPU name. Permissible values for this option are: @samp{spacemit-x100}, +@samp{spacemit-a100}, + @samp{arc-v-rhx-100-series}, @samp{generic-ooo}, diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-spacemit-a100.c b/gcc/testsuite/gcc.target/riscv/mcpu-spacemit-a100.c new file mode 100644 index 000000000000..6aada02c3eab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-spacemit-a100.c @@ -0,0 +1,80 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=spacemit-a100" { target { rv64 } } } */ +/* Spacemit A100 => rva23u64_zfh_zbc_zbkc_zfbfmin_smepmp_smnpm_smstateen_ + * sscofpmf_ssnpm_sspm_ssstateen_sstc_svinval_svnapot_svpbmt_zifencei_zvfh_ + * zvfbfwma_zvkng_zvknha_zvknc_zvksc_zvksg_zvl1024b_xsmtvdotii + */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && !defined(__riscv_h) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_v) \ + && defined(__riscv_zic64b) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zfhmin) \ + && defined(__riscv_ziccamoa) \ + && defined(__riscv_ziccif) \ + && defined(__riscv_zicclsm) \ + && defined(__riscv_ziccrse) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintntl) \ + && defined(__riscv_svpbmt) \ + && defined(__riscv_smepmp) \ + && defined(__riscv_sstc) \ + && defined(__riscv_sscofpmf) \ + && defined(__riscv_zicond) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_za64rs) \ + && defined(__riscv_zkt) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zbkc) \ + && defined(__riscv_zvfh) \ + && defined(__riscv_zvfhmin) \ + && defined(__riscv_zvl1024b) \ + && defined(__riscv_zfa) \ + && defined(__riscv_zca) \ + && defined(__riscv_zcb) \ + && defined(__riscv_zcd) \ + && defined(__riscv_zvbb) \ + && defined(__riscv_zvkng) \ + && defined(__riscv_zvknha) \ + && defined(__riscv_smstateen) \ + && defined(__riscv_ssstateen) \ + && defined(__riscv_zfbfmin) \ + && defined(__riscv_zvfbfmin) \ + && defined(__riscv_zvfbfwma) \ + && defined(__riscv_zimop) \ + && defined(__riscv_zcmop) \ + && defined(__riscv_smnpm) \ + && defined(__riscv_ssnpm) \ + && defined(__riscv_sspm) \ + && defined(__riscv_zawrs) \ + && defined(__riscv_zvbc) \ + && defined(__riscv_zvknc) \ + && defined(__riscv_zvksc) \ + && defined(__riscv_zvksg) \ + && defined(__riscv_supm) \ + && defined(__riscv_xsmtvdotii)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +}
