https://gcc.gnu.org/g:69d8365be181d6d62cf1c5e3a7dcd2548e1e74c6
commit 69d8365be181d6d62cf1c5e3a7dcd2548e1e74c6 Author: Avinash Jayakar <[email protected]> Date: Thu Jul 2 14:47:50 2026 +0530 rs6000: Corrections for the wD constraint implementation Removed the predicate accumulator_operand since it is not needed for now. Map the constraint to the newly added DMR_REGS reg class. Updated doc files accordingly. Diff: --- gcc/config/rs6000/constraints.md | 2 +- gcc/config/rs6000/predicates.md | 18 ------------------ gcc/config/rs6000/rs6000.cc | 6 +++--- gcc/config/rs6000/rs6000.h | 4 +++- gcc/doc/md.texi | 2 +- 5 files changed, 8 insertions(+), 24 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 6bb64d55b2d0..b62f6b4543d0 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -100,7 +100,7 @@ @code{NO_REGS}.") (define_register_constraint "wD" "rs6000_constraints[RS6000_CONSTRAINT_wD]" - "@internal 1024 bit accumulator register.") + "@internal Dense math register.") ;; wB needs ISA 2.07 VUPKHSW (define_constraint "wB" diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index e1cda4f8e72c..4162c22f8f68 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -163,24 +163,6 @@ return VINT_REGNO_P (REGNO (op)); }) -;; Return 1 if op is an accumulator. On power10/11 systems, the accumulators -;; overlap with the FPRs. -(define_predicate "accumulator_operand" - (match_operand 0 "register_operand") -{ - if (SUBREG_P (op)) - op = SUBREG_REG (op); - - if (!REG_P (op)) - return 0; - - if (!HARD_REGISTER_P (op)) - return 1; - - int r = REGNO (op); - return FP_REGNO_P (r) && (r & 3) == 0; -}) - ;; Return 1 if op is a vector register to do logical operations on (and, or, ;; xor, etc.) (define_predicate "vlogical_operand" diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index db54720f61c8..513adf02913f 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -2973,7 +2973,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) wn - always NO_REGS. wr - GPR if 64-bit mode is permitted. wx - Float register if we can do 32-bit int stores. - wD - Dense math accumulator if DMF, else float register. */ + wD - Dense math register if DMF enabled. */ if (TARGET_HARD_FLOAT) rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; @@ -2981,8 +2981,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS; if (TARGET_VSX) rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS; - if (TARGET_MMA) - rs6000_constraints[RS6000_CONSTRAINT_wD] = FLOAT_REGS; + if (TARGET_DMF) + rs6000_constraints[RS6000_CONSTRAINT_wD] = DMR_REGS; if (TARGET_POWERPC64) { diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 74d7db69f0bd..f3ea2e9659a4 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1073,6 +1073,7 @@ enum reg_class FLOAT_REGS, ALTIVEC_REGS, VSX_REGS, + DMR_REGS, VRSAVE_REGS, VSCR_REGS, GEN_OR_FLOAT_REGS, @@ -1102,6 +1103,7 @@ enum reg_class "FLOAT_REGS", \ "ALTIVEC_REGS", \ "VSX_REGS", \ + "DMR_REGS", \ "VRSAVE_REGS", \ "VSCR_REGS", \ "GEN_OR_FLOAT_REGS", \ @@ -1187,7 +1189,7 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ - RS6000_CONSTRAINT_wD, /* Accumulator registers. */ + RS6000_CONSTRAINT_wD, /* Dense math registers. */ RS6000_CONSTRAINT_MAX }; diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 0ff5f51e5c13..ed36f4bbfa8b 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3298,7 +3298,7 @@ Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}. Signed 5-bit constant integer that can be loaded into an Altivec register. @item wD -Accumulator register if @option{-mma} is used; otherwise, @code{NO_REGS}. +Dense math register if @option{-mdense-math} is used; otherwise, @code{NO_REGS}. @item wE Vector constant that can be loaded with the XXSPLTIB instruction.
