https://gcc.gnu.org/g:4508b52341080cd139639de834713bb756ca8176
commit r17-2147-g4508b52341080cd139639de834713bb756ca8176 Author: Oleg Endo <[email protected]> Date: Sat Jul 4 17:59:12 2026 +0900 SH: Remove remaining LRA transition helpers. gcc/ChangeLog: PR target/55212 * config/sh/sh-protos.h (sh_lra_p): Remove. (sh_legitimize_reload_address): Remove. * config/sh/sh.h (LEGITIMIZE_RELOAD_ADDRESS): Remove. * config/sh/sh.cc (sh_legitimize_reload_address): Remove. (prepare_move_operands, broken_move): Remove sh_lra_p uses. * config/sh/constraints.md (Rab, Rai, Ssd): Likewise. * config/sh/sh.md: Likewise. Remove reload-only *addsi3 patterns. gcc/testsuite/ChangeLog: PR target/55212 * gcc.target/sh/pr64366.c: Remove -mlra option. * g++.target/sh/torture/pr55212-c311.C: Likewise. * g++.target/sh/torture/pr55212-c333.C: Likewise. * g++.target/sh/torture/pr55212-c373.C: Likewise. * g++.target/sh/torture/pr55212-c384.C: Likewise. * g++.target/sh/torture/pr55212-c413.C: Likewise. Diff: --- gcc/config/sh/constraints.md | 29 +-- gcc/config/sh/sh-protos.h | 7 - gcc/config/sh/sh.cc | 88 +-------- gcc/config/sh/sh.h | 9 - gcc/config/sh/sh.md | 207 +++++++-------------- gcc/testsuite/g++.target/sh/torture/pr55212-c311.C | 2 +- gcc/testsuite/g++.target/sh/torture/pr55212-c333.C | 2 +- gcc/testsuite/g++.target/sh/torture/pr55212-c373.C | 2 +- gcc/testsuite/g++.target/sh/torture/pr55212-c384.C | 2 +- gcc/testsuite/g++.target/sh/torture/pr55212-c413.C | 2 +- gcc/testsuite/gcc.target/sh/pr64366.c | 2 +- 11 files changed, 85 insertions(+), 267 deletions(-) diff --git a/gcc/config/sh/constraints.md b/gcc/config/sh/constraints.md index 7b476dc6c389..0c998d2d0e3d 100644 --- a/gcc/config/sh/constraints.md +++ b/gcc/config/sh/constraints.md @@ -262,23 +262,15 @@ (match_test "~ival == 64") (match_test "~ival == 128")))) -;; FIXME: LRA and reload behavior differs in memory constraint handling. -;; For LRA memory address constraints need to narrow the register type -;; restrictions. It seems the address RTX validation is done slightly -;; differently. Remove the non-LRA paths eventually. +;; For LRA memory address constraints need to narrow the register type +;; restrictions. (define_constraint "Rab" "@internal address base register constraint" - (ior (and (match_test "sh_lra_p ()") - (match_test "MAYBE_BASE_REGISTER_RTX_P (op, false)")) - (and (match_test "!sh_lra_p ()") - (match_code "reg")))) + (match_test "MAYBE_BASE_REGISTER_RTX_P (op, false)")) (define_constraint "Rai" "@internal address index register constraint" - (ior (and (match_test "sh_lra_p ()") - (match_test "MAYBE_INDEX_REGISTER_RTX_P (op, false)")) - (and (match_test "!sh_lra_p ()") - (match_code "reg")))) + (match_test "MAYBE_INDEX_REGISTER_RTX_P (op, false)")) (define_memory_constraint "Sua" "A memory reference that allows simple register or post-inc addressing." @@ -310,15 +302,10 @@ (define_memory_constraint "Ssd" "A memory reference that excludes index and displacement addressing." - (ior (and (match_code "mem") - (match_test "! sh_lra_p ()") - (match_test "! satisfies_constraint_Sid (op)") - (match_test "! satisfies_constraint_Sdd (op)")) - (and (match_code "mem") - (match_test "sh_lra_p ()") - (ior (match_test "satisfies_constraint_Rab (XEXP (op, 0))") - (and (ior (match_code "pre_dec" "0") (match_code "post_inc" "0")) - (match_test "satisfies_constraint_Rab (XEXP (XEXP (op, 0), 0))")))))) + (and (match_code "mem") + (ior (match_test "satisfies_constraint_Rab (XEXP (op, 0))") + (and (ior (match_code "pre_dec" "0") (match_code "post_inc" "0")) + (match_test "satisfies_constraint_Rab (XEXP (XEXP (op, 0), 0))"))))) (define_memory_constraint "Sbv" "A memory reference, as used in SH2A bclr.b, bset.b, etc." diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h index c040af244706..7379649150f7 100644 --- a/gcc/config/sh/sh-protos.h +++ b/gcc/config/sh/sh-protos.h @@ -41,12 +41,6 @@ extern rtx sh_fsca_int2sf (void); /* Declare functions defined in sh.cc and used in templates. */ -/* FIXME: sh_lra_p is for transional purposes only. Remove it eventually. */ -inline bool sh_lra_p (void) -{ - return true; -} - extern const char *output_branch (int, rtx_insn *, rtx *); extern const char *output_ieee_ccmpeq (rtx_insn *, rtx *); extern const char *output_branchy_insn (enum rtx_code, const char *, @@ -61,7 +55,6 @@ extern int sh_loop_align (rtx_insn *); extern bool fp_zero_operand (rtx); extern bool fp_one_operand (rtx); extern bool sh_legitimate_index_p (machine_mode, rtx, bool, bool); -extern bool sh_legitimize_reload_address (rtx *, machine_mode, int, int); extern rtx legitimize_pic_address (rtx, machine_mode, rtx); extern bool nonpic_symbol_mentioned_p (rtx); extern void output_pic_addr_const (FILE *, rtx); diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc index b6ea720acfd0..9e488bfe6abc 100644 --- a/gcc/config/sh/sh.cc +++ b/gcc/config/sh/sh.cc @@ -1657,8 +1657,7 @@ prepare_move_operands (rtx operands[], machine_mode mode) in some situation. It isn't the case for SH in the problematic case. We can pre-allocate R0 for that index term to avoid the issue. See PR target/66591. */ - else if (sh_lra_p () - && ! TARGET_SH2A + else if (! TARGET_SH2A && ((REG_P (operands[0]) && MEM_P (operands[1])) || (REG_P (operands[1]) && MEM_P (operands[0])))) { @@ -4820,17 +4819,8 @@ broken_move (rtx_insn *insn) && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE && (fp_zero_operand (SET_SRC (pat)) || fp_one_operand (SET_SRC (pat))) - /* In general we don't know the current setting of fpscr, so - disable fldi. - There is an exception if this was a register-register move - before reload - and hence it was ascertained that we have - single precision setting - and in a post-reload optimization - we changed this to do a constant load. In that case - we don't have an r0 clobber, hence we must use fldi. */ - && (TARGET_FMOVD - || sh_lra_p () - || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0)) - == SCRATCH)) + /* fldi can materialize the fp constants 0 and 1 directly in + an fp register, so such a move is not broken. */ && REG_P (SET_DEST (pat)) && FP_REGISTER_P (REGNO (SET_DEST (pat)))) && ! (TARGET_SH2A @@ -9273,78 +9263,6 @@ sh_legitimize_address (rtx x, rtx oldx, machine_mode mode) return x; } -/* Attempt to replace *p, which is an address that needs reloading, with - a valid memory address for an operand of mode MODE. - Like for sh_legitimize_address, for the SH we try to get a normal form - of the address. That will allow inheritance of the address reloads. */ -bool -sh_legitimize_reload_address (rtx *p, machine_mode mode, int opnum, - int itype) -{ - enum reload_type type = (enum reload_type) itype; - const int mode_sz = GET_MODE_SIZE (mode); - - if (sh_lra_p ()) - return false; - - if (GET_CODE (*p) == PLUS && CONST_INT_P (XEXP (*p, 1)) - && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true)) - { - const HOST_WIDE_INT offset = INTVAL (XEXP (*p, 1)); - struct disp_adjust adj = sh_find_mov_disp_adjust (mode, offset); - - if (TARGET_SH2A && mode == DFmode && (offset & 0x7)) - { - push_reload (*p, NULL_RTX, p, NULL, - BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); - return true; - } - - if (TARGET_SH2E && mode == SFmode) - { - *p = copy_rtx (*p); - push_reload (*p, NULL_RTX, p, NULL, - BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); - return true; - } - - /* FIXME: Do not allow to legitimize QImode and HImode displacement - moves because then reload has a problem figuring the constraint - that the move insn target/source reg must be R0. - Or maybe some handling is wrong in sh_secondary_reload for this - to work properly? */ - if ((mode_sz == 4 || mode_sz == 8) - && ! (TARGET_SH4 && mode == DFmode) - && adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX) - { - rtx sum = gen_rtx_PLUS (Pmode, XEXP (*p, 0), adj.offset_adjust); - *p = gen_rtx_PLUS (Pmode, sum, adj.mov_disp); - push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL, - BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); - return true; - } - } - - /* We must re-recognize what we created before. */ - if (GET_CODE (*p) == PLUS - && (mode_sz == 4 || mode_sz == 8) - && GET_CODE (XEXP (*p, 0)) == PLUS - && CONST_INT_P (XEXP (XEXP (*p, 0), 1)) - && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p, 0), 0), true) - && CONST_INT_P (XEXP (*p, 1)) - && ! (TARGET_SH2E && mode == SFmode)) - { - /* Because this address is so complex, we know it must have - been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, - it is already unshared, and needs no further unsharing. */ - push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL, - BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); - return true; - } - - return false; -} - /* In the name of slightly smaller debug output, and to cater to general assembler lossage, recognize various UNSPEC sequences and turn them back into a direct symbol reference. */ diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index b0740adb82b4..9b2ed6a33db8 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -1402,15 +1402,6 @@ extern bool current_function_interrupt; #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false) #endif - -/* A C compound statement that attempts to replace X, which is an address - that needs reloading, with a valid memory address for an operand of - mode MODE. WIN is a C statement label elsewhere in the code. */ -#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ - do { \ - if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \ - goto WIN; \ - } while (0) /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index d5f6c80030a6..18744d3a75d1 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -1785,7 +1785,7 @@ { if (!arith_operand (operands[2], SImode)) { - if (!sh_lra_p () || reg_overlap_mentioned_p (operands[0], operands[1])) + if (reg_overlap_mentioned_p (operands[0], operands[1])) { emit_insn (gen_addsi3_scr (operands[0], operands[1], operands[2])); DONE; @@ -1801,16 +1801,13 @@ ;; copy or constant load before the actual add insn. ;; Use u constraint for that case to avoid the invalid value in the stack ;; pointer. -;; This also results in better code when LRA is not used. However, we have -;; to use different sets of patterns and the order of these patterns is -;; important. ;; In some cases the constant zero might end up in operands[2] of the ;; patterns. We have to accept that and convert it into a reg-reg move. (define_insn_and_split "*addsi3_compact_lra" [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u") (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r") (match_operand:SI 2 "arith_or_int_operand" "rI08,rn")))] - "TARGET_SH1 && sh_lra_p () + "TARGET_SH1 && (! reg_overlap_mentioned_p (operands[0], operands[1]) || arith_operand (operands[2], SImode))" "@ @@ -1870,64 +1867,6 @@ } [(set_attr "type" "arith")]) -;; Old reload might generate add insns directly (not through the expander) for -;; address register calculations when reloading, in which case it won't try -;; the addsi_scr pattern. Because reload will sometimes try to validate -;; the generated insns and their constraints, this pattern must be -;; recognizable during and after reload. However, when reload generates -;; address register calculations for the stack pointer, we don't allow this -;; pattern. This will make reload prefer using indexed @(reg + reg) address -;; modes when the displacement of a @(disp + reg) doesn't fit. -(define_insn_and_split "*addsi3" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (plus:SI (match_operand:SI 1 "arith_reg_operand" "r") - (match_operand:SI 2 "arith_or_int_operand" "rn")))] - "TARGET_SH1 && !sh_lra_p () - && (reload_completed || reload_in_progress) - && !reg_overlap_mentioned_p (operands[0], operands[1]) - && (!reload_in_progress - || ((!REG_P (operands[1]) || REGNO (operands[1]) != SP_REG) - && (!REG_P (operands[2]) || REGNO (operands[2]) != SP_REG)))" - "#" - "&& 1" - [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] -{ - if (operands[2] == const0_rtx) - { - emit_move_insn (operands[0], operands[1]); - DONE; - } - - if (CONST_INT_P (operands[2])) - { - if (satisfies_constraint_I08 (operands[2])) - emit_move_insn (operands[0], operands[1]); - else - { - emit_move_insn (operands[0], operands[2]); - operands[2] = operands[1]; - } - } - else if (!reg_overlap_mentioned_p (operands[0], operands[2])) - emit_move_insn (operands[0], operands[1]); - else - operands[2] = operands[1]; -}) - -(define_insn_and_split "*addsi3" - [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") - (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r") - (match_operand:SI 2 "arith_operand" "rI08,Z")))] - "TARGET_SH1 && !sh_lra_p ()" - "@ - add %2,%0 - #" - "&& operands[2] == const0_rtx" - [(set (match_dup 0) (match_dup 1))] -{ -} - [(set_attr "type" "arith")]) - ;; ------------------------------------------------------------------------- ;; Subtraction instructions ;; ------------------------------------------------------------------------- @@ -4839,7 +4778,6 @@ register operand for the QI/HImode load. See the comment in sh.cc:prepare_move_operand and PR target/55212. */ if (! lra_in_progress && ! reload_completed - && sh_lra_p () && ! TARGET_SH2A && arith_reg_dest (operands[0], <MODE>mode) && short_displacement_mem_operand (operands[1], <MODE>mode)) @@ -4909,7 +4847,7 @@ (sign_extend:SI (match_operand:QIHI 1 "short_displacement_mem_operand" "m"))) (clobber (reg:SI R0_REG))] - "TARGET_SH1 && ! TARGET_SH2A && sh_lra_p ()" + "TARGET_SH1 && ! TARGET_SH2A" "#" "&& 1" [(set (match_dup 2) (sign_extend:SI (match_dup 1))) @@ -5410,7 +5348,6 @@ } if (! lra_in_progress && ! reload_completed - && sh_lra_p () && ! TARGET_SH2A && arith_reg_operand (operands[1], <MODE>mode) && satisfies_constraint_Sid (operands[0])) @@ -5433,7 +5370,7 @@ [(set (mem:QIHI (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r") (match_operand:SI 1 "hard_reg_r0" "z"))) (match_operand:QIHI 2 "arith_reg_operand" "r"))] - "TARGET_SH1 && ! TARGET_SH2A && sh_lra_p ()" + "TARGET_SH1 && ! TARGET_SH2A" "mov.<bw> %2,@(%1,%0)" [(set_attr "type" "store")]) @@ -5442,7 +5379,7 @@ (match_operand:SI 1 "arith_reg_operand" "^zr"))) (match_operand:QIHI 2 "arith_reg_operand" "r")) (clobber (reg:SI R0_REG))] - "TARGET_SH1 && ! TARGET_SH2A && sh_lra_p ()" + "TARGET_SH1 && ! TARGET_SH2A" "#" "&& 1" [(set (match_dup 3) (match_dup 1)) @@ -5745,7 +5682,7 @@ (match_operand:DF 1 "const_double_operand" "F")) (use (reg:SI FPSCR_MODES_REG)) (clobber (reg:SI R0_REG))] - "TARGET_FPU_DOUBLE && sh_lra_p ()" + "TARGET_FPU_DOUBLE" "#" [(set_attr "type" "pcfload") (set (attr "length") (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8))) @@ -5896,7 +5833,7 @@ [(set (match_operand:SF 0 "register_operand") (match_operand:SF 1 "register_operand")) (use (reg:SI FPSCR_MODES_REG))] - "TARGET_SH2E && sh_lra_p () && reload_completed + "TARGET_SH2E && reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])" [(set (match_dup 0) (match_dup 0))]) @@ -6144,9 +6081,7 @@ prepare_move_operands (operands, DFmode); if (TARGET_FPU_DOUBLE) { - if (sh_lra_p () - && (GET_CODE (operands[1]) == CONST_DOUBLE - && REG_P (operands[0]))) + if (GET_CODE (operands[1]) == CONST_DOUBLE && REG_P (operands[0])) { emit_insn (gen_movdf_i4_F_z (operands[0], operands[1])); DONE; @@ -6286,7 +6221,7 @@ (match_operand:SF 1 "general_movsrc_operand" " f,r,G,H,m,f,FQ,m,r,y,f,>,y,r,y,>,y")) (use (reg:SI FPSCR_MODES_REG))] - "TARGET_SH2E && sh_lra_p () + "TARGET_SH2E && ! sh_movsf_ie_y_split_p (operands[0], operands[1]) && (arith_reg_operand (operands[0], SFmode) || fpul_operand (operands[0], SFmode) @@ -6362,7 +6297,7 @@ (match_operand:SF 1 "arith_reg_operand" "f,r,fr")) (use (reg:SI FPSCR_MODES_REG)) (clobber (match_scratch:SF 2 "=X,X,y"))] - "TARGET_SH2E && sh_lra_p ()" + "TARGET_SH2E" "@ fmov %1,%0 mov %1,%0 @@ -6391,7 +6326,7 @@ (match_operand:SF 1 "const_double_operand" "F")) (use (reg:SI FPSCR_MODES_REG)) (clobber (reg:SI R0_REG))] - "TARGET_SH2E && sh_lra_p ()" + "TARGET_SH2E" "#" [(set_attr "type" "pcfload") (set_attr "length" "4")]) @@ -6401,7 +6336,7 @@ (match_operand:SF 1 "pc_relative_load_operand" "Q")) (use (reg:SI FPSCR_MODES_REG)) (clobber (reg:SI R0_REG))] - "TARGET_SH2E && sh_lra_p ()" + "TARGET_SH2E" "#" [(set_attr "type" "pcfload") (set_attr "length" "4")]) @@ -6411,7 +6346,7 @@ (match_operand:SF 1 "arith_reg_operand" "rf")) (use (reg:SI FPSCR_MODES_REG)) (clobber (reg:SI FPUL_REG))] - "TARGET_SH2E && sh_lra_p ()" + "TARGET_SH2E" "#" [(set_attr "type" "*") (set_attr "length" "4")]) @@ -6441,7 +6376,7 @@ (match_operand:SI 1 "hard_reg_r0" "z"))) (match_operand:SF 2 "fp_arith_reg_operand" "f")) (use (reg:SI FPSCR_MODES_REG))] - "TARGET_SH2E && sh_lra_p ()" + "TARGET_SH2E" "fmov.s %2,@(%1,%0)" [(set_attr "type" "store")]) @@ -6451,7 +6386,7 @@ (match_operand:SF 2 "fp_arith_reg_operand" "f")) (use (reg:SI FPSCR_MODES_REG)) (clobber (reg:SI R0_REG))] - "TARGET_SH2E && sh_lra_p ()" + "TARGET_SH2E" "#" "&& 1" [(set (match_dup 3) (match_dup 1)) @@ -6471,7 +6406,7 @@ (mem:SF (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r") (match_operand:SI 2 "hard_reg_r0" "z")))) (use (reg:SI FPSCR_MODES_REG))] - "TARGET_SH2E && sh_lra_p ()" + "TARGET_SH2E" "fmov.s @(%2,%1),%0" [(set_attr "type" "load")]) @@ -6481,7 +6416,7 @@ (match_operand:SI 2 "arith_reg_operand" "^zr")))) (use (reg:SI FPSCR_MODES_REG)) (clobber (reg:SI R0_REG))] - "TARGET_SH2E && sh_lra_p ()" + "TARGET_SH2E" "#" "&& 1" [(set (match_dup 3) (match_dup 2)) @@ -6680,66 +6615,60 @@ prepare_move_operands (operands, SFmode); if (TARGET_SH2E) { - if (sh_lra_p ()) + if (GET_CODE (operands[0]) == SCRATCH) + DONE; + if (! lra_in_progress && ! reload_completed + && fp_arith_reg_operand (operands[1], SFmode) + && satisfies_constraint_Sid (operands[0])) { - if (GET_CODE (operands[0]) == SCRATCH) - DONE; - if (! lra_in_progress && ! reload_completed - && fp_arith_reg_operand (operands[1], SFmode) - && satisfies_constraint_Sid (operands[0])) - { - rtx adr = XEXP (operands[0], 0); - rtx base = XEXP (adr, 0); - rtx idx = XEXP (adr, 1); - emit_insn (gen_movsf_ie_store_mem_index (base, idx, operands[1])); - DONE; - } - if (! lra_in_progress && ! reload_completed - && fp_arith_reg_operand (operands[0], SFmode) - && satisfies_constraint_Sid (operands[1])) - { - rtx adr = XEXP (operands[1], 0); - rtx base = XEXP (adr, 0); - rtx idx = XEXP (adr, 1); - emit_insn (gen_movsf_ie_load_mem_index (operands[0], base, idx)); - DONE; - } - /* reg from/to multiword subreg may be splitted to several reg from/to - subreg of SImode by subreg1 pass. This confuses our splitted - movsf logic for LRA and will end up in bad code or ICE. Use a special - pattern so that LRA can optimize this case. */ - if (! lra_in_progress && ! reload_completed - && sh_movsf_ie_subreg_multiword_p (operands[0], operands[1])) - { - emit_insn (gen_movsf_ie_rffr (operands[0], operands[1])); - DONE; - } - if (GET_CODE (operands[1]) == CONST_DOUBLE - && ! satisfies_constraint_G (operands[1]) - && ! satisfies_constraint_H (operands[1]) - && REG_P (operands[0])) - { - if (lra_in_progress) - emit_insn (gen_movsf_ie (operands[0], operands[1])); - else - emit_insn (gen_movsf_ie_F_z (operands[0], operands[1])); - } - else if (REG_P (operands[0]) && REGNO (operands[0]) == FPUL_REG - && satisfies_constraint_Q (operands[1])) - emit_insn (gen_movsf_ie_Q_z (operands[0], operands[1])); - else if (sh_movsf_ie_y_split_p (operands[0], operands[1])) - { - if (lra_in_progress) - emit_insn (gen_movsf_ie (operands[0], operands[1])); - else - emit_insn (gen_movsf_ie_y (operands[0], operands[1])); - } - else - emit_insn (gen_movsf_ie_ra (operands[0], operands[1])); + rtx adr = XEXP (operands[0], 0); + rtx base = XEXP (adr, 0); + rtx idx = XEXP (adr, 1); + emit_insn (gen_movsf_ie_store_mem_index (base, idx, operands[1])); DONE; } - - emit_insn (gen_movsf_ie (operands[0], operands[1])); + if (! lra_in_progress && ! reload_completed + && fp_arith_reg_operand (operands[0], SFmode) + && satisfies_constraint_Sid (operands[1])) + { + rtx adr = XEXP (operands[1], 0); + rtx base = XEXP (adr, 0); + rtx idx = XEXP (adr, 1); + emit_insn (gen_movsf_ie_load_mem_index (operands[0], base, idx)); + DONE; + } + /* reg from/to multiword subreg may be splitted to several reg from/to + subreg of SImode by subreg1 pass. This confuses our splitted + movsf logic for LRA and will end up in bad code or ICE. Use a special + pattern so that LRA can optimize this case. */ + if (! lra_in_progress && ! reload_completed + && sh_movsf_ie_subreg_multiword_p (operands[0], operands[1])) + { + emit_insn (gen_movsf_ie_rffr (operands[0], operands[1])); + DONE; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE + && ! satisfies_constraint_G (operands[1]) + && ! satisfies_constraint_H (operands[1]) + && REG_P (operands[0])) + { + if (lra_in_progress) + emit_insn (gen_movsf_ie (operands[0], operands[1])); + else + emit_insn (gen_movsf_ie_F_z (operands[0], operands[1])); + } + else if (REG_P (operands[0]) && REGNO (operands[0]) == FPUL_REG + && satisfies_constraint_Q (operands[1])) + emit_insn (gen_movsf_ie_Q_z (operands[0], operands[1])); + else if (sh_movsf_ie_y_split_p (operands[0], operands[1])) + { + if (lra_in_progress) + emit_insn (gen_movsf_ie (operands[0], operands[1])); + else + emit_insn (gen_movsf_ie_y (operands[0], operands[1])); + } + else + emit_insn (gen_movsf_ie_ra (operands[0], operands[1])); DONE; } }) diff --git a/gcc/testsuite/g++.target/sh/torture/pr55212-c311.C b/gcc/testsuite/g++.target/sh/torture/pr55212-c311.C index cc31dbcc4436..1edf9623f75a 100644 --- a/gcc/testsuite/g++.target/sh/torture/pr55212-c311.C +++ b/gcc/testsuite/g++.target/sh/torture/pr55212-c311.C @@ -1,4 +1,4 @@ -/* { dg-additional-options "-mlra -fpic" } */ +/* { dg-additional-options "-fpic" } */ /* { dg-do compile } */ diff --git a/gcc/testsuite/g++.target/sh/torture/pr55212-c333.C b/gcc/testsuite/g++.target/sh/torture/pr55212-c333.C index afab629cdf2d..31e636acb42c 100644 --- a/gcc/testsuite/g++.target/sh/torture/pr55212-c333.C +++ b/gcc/testsuite/g++.target/sh/torture/pr55212-c333.C @@ -1,4 +1,4 @@ -/* { dg-additional-options "-std=c++20 -mlra -fpic -w " } */ +/* { dg-additional-options "-std=c++20 -fpic -w " } */ /* { dg-do compile } */ typedef unsigned int size_t; diff --git a/gcc/testsuite/g++.target/sh/torture/pr55212-c373.C b/gcc/testsuite/g++.target/sh/torture/pr55212-c373.C index d1f30cb93c42..ecf731a41eaa 100644 --- a/gcc/testsuite/g++.target/sh/torture/pr55212-c373.C +++ b/gcc/testsuite/g++.target/sh/torture/pr55212-c373.C @@ -1,4 +1,4 @@ -/* { dg-additional-options "-std=c++20 -mlra -fpic -w " } */ +/* { dg-additional-options "-std=c++20 -fpic -w " } */ /* { dg-do compile } */ namespace std { diff --git a/gcc/testsuite/g++.target/sh/torture/pr55212-c384.C b/gcc/testsuite/g++.target/sh/torture/pr55212-c384.C index f46136489b58..972f258c6916 100644 --- a/gcc/testsuite/g++.target/sh/torture/pr55212-c384.C +++ b/gcc/testsuite/g++.target/sh/torture/pr55212-c384.C @@ -1,4 +1,4 @@ -/* { dg-additional-options "-std=c++20 -mlra -fpic -w " } */ +/* { dg-additional-options "-std=c++20 -fpic -w " } */ /* { dg-do compile } */ typedef unsigned int size_t; diff --git a/gcc/testsuite/g++.target/sh/torture/pr55212-c413.C b/gcc/testsuite/g++.target/sh/torture/pr55212-c413.C index 13eb1ff4d894..9773686825a2 100644 --- a/gcc/testsuite/g++.target/sh/torture/pr55212-c413.C +++ b/gcc/testsuite/g++.target/sh/torture/pr55212-c413.C @@ -1,4 +1,4 @@ -/* { dg-additional-options "-std=c++20 -mlra -fpic -w " } */ +/* { dg-additional-options "-std=c++20 -fpic -w " } */ /* { dg-do compile } */ struct Trans_NS_WTF_HashMap diff --git a/gcc/testsuite/gcc.target/sh/pr64366.c b/gcc/testsuite/gcc.target/sh/pr64366.c index 4fe29c38e912..f13fc9354700 100644 --- a/gcc/testsuite/gcc.target/sh/pr64366.c +++ b/gcc/testsuite/gcc.target/sh/pr64366.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mlra -std=gnu17" } */ +/* { dg-options "-O2 -std=gnu17" } */ typedef int int8_t __attribute__ ((__mode__ (__QI__))); typedef int int16_t __attribute__ ((__mode__ (__HI__)));
