https://gcc.gnu.org/g:a42df84117b9d20af02b40ada8f9875e51d971ab
commit a42df84117b9d20af02b40ada8f9875e51d971ab Author: Avinash Jayakar <[email protected]> Date: Mon Jul 6 15:34:30 2026 +0530 rs6000: Update wD constraint to mean [MMA->FPR] [DMF->DMR] If TARGET_DMF is enabled then wD constraint would mean the 1024 bit dense math registers. Otherwise, if only TARGET_MMA is enabled it maps to FPR registers. If both are enabled, then DMR is used. Diff: --- gcc/config/rs6000/constraints.md | 3 ++- gcc/config/rs6000/predicates.md | 19 +++++++++++++++++++ gcc/config/rs6000/rs6000.cc | 4 +++- gcc/config/rs6000/rs6000.h | 2 +- gcc/doc/md.texi | 2 +- 5 files changed, 26 insertions(+), 4 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index b62f6b4543d0..4b2e703f0497 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -100,7 +100,8 @@ @code{NO_REGS}.") (define_register_constraint "wD" "rs6000_constraints[RS6000_CONSTRAINT_wD]" - "@internal Dense math register.") + "@internal Floating point register @code{FPR} if TARGET_MMA is enabled. + 1024 bit Dense math register @code{DMR} if TARGET_DMF is enabled.") ;; wB needs ISA 2.07 VUPKHSW (define_constraint "wB" diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 4162c22f8f68..63588ff99613 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -163,6 +163,25 @@ return VINT_REGNO_P (REGNO (op)); }) +;; Return 1 if op is an accumulator. On power10/11 systems, the accumulators +;; overlap with the FPRs. On future systems, it will be a separate set of +;; registers. +(define_predicate "accumulator_operand" + (match_operand 0 "register_operand") +{ + if (SUBREG_P (op)) + op = SUBREG_REG (op); + + if (!REG_P (op)) + return 0; + + if (!HARD_REGISTER_P (op)) + return 1; + + int r = REGNO (op); + return TARGET_DMF ? DMR_REGNO_P (r) : (FP_REGNO_P (r) && (r & 3) == 0); +}) + ;; Return 1 if op is a vector register to do logical operations on (and, or, ;; xor, etc.) (define_predicate "vlogical_operand" diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index e656470abfff..c2302a253379 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3020,7 +3020,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) wn - always NO_REGS. wr - GPR if 64-bit mode is permitted. wx - Float register if we can do 32-bit int stores. - wD - Dense math register if DMF enabled. */ + wD - 1024 bit DMR if TARGET_DMF is enabled, else float register. */ if (TARGET_HARD_FLOAT) rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; @@ -3030,6 +3030,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS; if (TARGET_DMF) rs6000_constraints[RS6000_CONSTRAINT_wD] = DMR_REGS; + else if (TARGET_MMA) + rs6000_constraints[RS6000_CONSTRAINT_wD] = FLOAT_REGS; if (TARGET_POWERPC64) { diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 0ecb15d021f5..f002235e8e01 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1202,7 +1202,7 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ - RS6000_CONSTRAINT_wD, /* Dense math registers. */ + RS6000_CONSTRAINT_wD, /* Accumulator registers. */ RS6000_CONSTRAINT_MAX }; diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index ed36f4bbfa8b..0ff5f51e5c13 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3298,7 +3298,7 @@ Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}. Signed 5-bit constant integer that can be loaded into an Altivec register. @item wD -Dense math register if @option{-mdense-math} is used; otherwise, @code{NO_REGS}. +Accumulator register if @option{-mma} is used; otherwise, @code{NO_REGS}. @item wE Vector constant that can be loaded with the XXSPLTIB instruction.
