https://gcc.gnu.org/g:dcc27c76c3d84d903a725739cd1d452fa15b21c6
commit r17-2170-gdcc27c76c3d84d903a725739cd1d452fa15b21c6 Author: Mark Zhuang <[email protected]> Date: Mon Jul 6 08:41:11 2026 -0600 [PATCH] RISC-V: Update spacemit-x60 to use rva22u64 profile From: Mark Zhuang <[email protected]> Replace the hand-written base with rva22u64 profile shorthand, aligning with RVA22 standard and X60 hardware capabilities. This also adds previously unlisted extensions. gcc/ChangeLog: * config/riscv/riscv-cores.def (spacemit-x60): Use rva22u64 profile shorthand, add missing entries. gcc/testsuite/ * gcc.target/riscv/mcpu-spacemit-x60.c: New test. Diff: --- gcc/config/riscv/riscv-cores.def | 5 +- gcc/testsuite/gcc.target/riscv/mcpu-spacemit-x60.c | 57 ++++++++++++++++++++++ 2 files changed, 60 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 57c8e76b2bd2..86d2175091ea 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -219,8 +219,9 @@ RISCV_CORE("andes-nx45", "rv64imc_zicsr_zifencei_xandesperf", "andes-45- RISCV_CORE("andes-a45", "rv32imafdc_zicsr_zifencei_xandesperf", "andes-45-series") RISCV_CORE("andes-ax45", "rv64imafdc_zicsr_zifencei_xandesperf", "andes-45-series") -RISCV_CORE("spacemit-x60", "rv64imafdcv_zba_zbb_zbc_zbs_zicboz_zicond_" - "zbkc_zfh_zvfh_zvkt_zvl256b_sscofpmf_xsmtvdot", +RISCV_CORE("spacemit-x60", "rva22u64_v_zicond_zifencei_zihintntl_zihpm_zfh_zbc_" + "zbkc_zvfh_zvfhmin_zvkt_zvl256b_smepmp_sscofpmf_sstc_" + "svinval_svnapot_svpbmt_xsmtvdot", "spacemit-x60") RISCV_CORE("spacemit-x100", "rva23s64_smepmp_smnpm_smstateen_sspm_zbc_zbkc_" diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-spacemit-x60.c b/gcc/testsuite/gcc.target/riscv/mcpu-spacemit-x60.c new file mode 100644 index 000000000000..21a4c65c05ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-spacemit-x60.c @@ -0,0 +1,57 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=spacemit-x60" { target { rv64 } } } */ +/* Spacemit X60 => rva22u64_v_zicond_zifencei_zihintntl_zihpm_zfh_zbc_ + * zbkc_zvfh_zvfhmin_zvkt_zvl256b_smepmp_sscofpmf_sstc_svinval_svnapot_ + * svpbmt_xsmtvdot + */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_v) \ + && defined(__riscv_zic64b) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zfhmin) \ + && defined(__riscv_ziccamoa) \ + && defined(__riscv_ziccif) \ + && defined(__riscv_zicclsm) \ + && defined(__riscv_ziccrse) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintntl) \ + && defined(__riscv_svpbmt) \ + && defined(__riscv_smepmp) \ + && defined(__riscv_sstc) \ + && defined(__riscv_sscofpmf) \ + && defined(__riscv_zicond) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_za64rs) \ + && defined(__riscv_zkt) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zbkc) \ + && defined(__riscv_zvfh) \ + && defined(__riscv_zvfhmin) \ + && defined(__riscv_zvkt) \ + && defined(__riscv_zvl256b) \ + && defined(__riscv_xsmtvdot)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +}
