https://gcc.gnu.org/g:413d90e7515b571bbbf33475695ba042cf5890a6
commit r17-2175-g413d90e7515b571bbbf33475695ba042cf5890a6 Author: Jim Lin <[email protected]> Date: Mon Jul 6 09:37:25 2026 -0600 [PATCH] RISC-V: Skip shift-shift-7.c under -Og At -Og the a << 1 is kept as a separate slliw instead of being folded into the zero_extendsidi2_shifted sequence, so the "slli" regex matches both slliw and slli and the scan-assembler-times "slli" 1 check fails. Skip the test under -Og. gcc/testsuite/ChangeLog: * gcc.target/riscv/shift-shift-7.c: Skip under -Og. Diff: --- gcc/testsuite/gcc.target/riscv/shift-shift-7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-7.c b/gcc/testsuite/gcc.target/riscv/shift-shift-7.c index 3ecd9ebdc39c..8fe9143960e6 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-7.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-7.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gc -mabi=lp64" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ /* Test for zero_extendsidi2_shifted handling arbitrary mask widths (not just 32 bits). */
