https://gcc.gnu.org/g:3df8eca700dd8d4985e5f87b5e0d5523c2f4892c

commit 3df8eca700dd8d4985e5f87b5e0d5523c2f4892c
Author: Kishan Parmar <[email protected]>
Date:   Wed Jul 8 22:56:20 2026 +0530

    MMA+: __builtin_mma_build_dmr does not build DMR correctly
    
    The vectors are placed at incorrect locations in the DMR register.
    This patch ensures that the DMR is populated correctly.
    Also fix testcase dmf-extract512.c.

Diff:
---
 gcc/config/rs6000/mma.md                         | 8 ++++----
 gcc/testsuite/gcc.target/powerpc/dmf-build-dmr.c | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 3328105fcd57..1026a5be8898 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -630,10 +630,10 @@
   rtx vp1 = gen_reg_rtx (OOmode);
   rtx vp2 = gen_reg_rtx (OOmode);
   rtx vp3 = gen_reg_rtx (OOmode);
-  emit_insn (gen_vsx_assemble_pair (vp0, operands[1], operands[2]));
-  emit_insn (gen_vsx_assemble_pair (vp1, operands[3], operands[4]));
-  emit_insn (gen_vsx_assemble_pair (vp2, operands[5], operands[6]));
-  emit_insn (gen_vsx_assemble_pair (vp3, operands[7], operands[8]));
+  emit_insn (gen_vsx_assemble_pair (vp0, operands[2], operands[1]));
+  emit_insn (gen_vsx_assemble_pair (vp1, operands[4], operands[3]));
+  emit_insn (gen_vsx_assemble_pair (vp2, operands[6], operands[5]));
+  emit_insn (gen_vsx_assemble_pair (vp3, operands[8], operands[7]));
   emit_insn (gen_dm_insert1024 (operands[0], vp0, vp1, vp2, vp3));
   DONE;
 })
diff --git a/gcc/testsuite/gcc.target/powerpc/dmf-build-dmr.c 
b/gcc/testsuite/gcc.target/powerpc/dmf-build-dmr.c
index 625b311acb9d..d5e85e64e27e 100644
--- a/gcc/testsuite/gcc.target/powerpc/dmf-build-dmr.c
+++ b/gcc/testsuite/gcc.target/powerpc/dmf-build-dmr.c
@@ -12,4 +12,4 @@ foo2 (__dmr1024 *dst, vec_t *src)
 }
 
 /* { dg-final { scan-assembler-times {\mdmxxinstdmr512\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mdmxxextfdmr512\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlxv\M} 8 } } */

Reply via email to