https://gcc.gnu.org/g:8a1346f379a15dc8b79e50656dc5d8728336231c
commit r17-2407-g8a1346f379a15dc8b79e50656dc5d8728336231c Author: H.J. Lu <[email protected]> Date: Mon Jul 13 09:12:13 2026 +0800 x86-64: Add missing SSE and AVX zero-extend patterns 1. Add round_zext and round_saeonly_zext to subst.md. 2. Use them to add missing SSE and AVX zero-extend patterns. 3. Add tests to check for newly added SSE and AVX zero-extend patterns. gcc/ PR target/126231 * config/i386/i386.md (*fix_trunc<mode>si_sse_zext): New. * config/i386/sse.md (*avx512fp16_vcvtsh2<sseintconvertsignprefix>si<round_zext_name>): Likewise. (*avx512fp16_vcvtsh2<sseintconvertsignprefix>si_2_zext): Likewise. (*unspec_avx512fp16_fix<vcvtt_uns_suffix>_truncsi2<round_saeonly_zext_name>): Likewise. (*sse_cvtss2si<round_zext_name>): Likewise. (*sse_cvtss2si_2_zext): Likewise. (*unspec_sse_cvttss2si<round_saeonly_zext_name>): Likewise. (*sse_cvttss2si<round_saeonly_zext_name>): Likewise. (*avx512f_vcvtss2usi<round_zext_name>): Likewise. (*unspec_avx512f_vcvttss2usi<round_saeonly_zext_name>): Likewise. (*avx512f_vcvttss2usi<round_saeonly_zext_name>): Likewise. (*avx512f_vcvtsd2usi<round_zext_name>): Likewise. (*unspec_avx512f_vcvttsd2usi<round_saeonly_zext_name>): Likewise. (*avx512f_vcvttsd2usi<round_saeonly_zext_name>): Likewise. (*sse2_cvtsd2si<round_zext_name>): Likewise. (*sse2_cvtsd2si_2_zext): Likewise. (*unspec_sse2_cvttsd2si<round_saeonly_zext_name>): Likewise. (*sse2_cvttsd2si<round_saeonly_zext_name>): Likewise. (*avx10_2_vcvttsd2<sat_cvt_sign_prefix>sissi<round_saeonly_zext_name>): Likewise. (*avx10_2_vcvttss2<sat_cvt_sign_prefix>sissi<round_saeonly_zext_name>): Likewise. * config/i386/subst.md (round_zext_name): Likewise. (round_zext_constraint): Likewise. (round_zext_constraint2): Likewise. (round_zext_nimm_predicate): Likewise. (round_zext_nimm_scalar_predicate): Likewise. (round_zext_op2): Likewise. (round_zext): Likewise. (round_saeonly_zext_name): Likewise. (round_saeonly_zext_constraint): Likewise. (round_saeonly_zext_constraint2): Likewise. (round_saeonly_zext_nimm_scalar_predicate): Likewise. (round_saeonly_zext_op2): Likewise. (round_saeonly_zext): Likewise. gcc/testsuite/ PR target/126231 * gcc.target/i386/zext-avx10-1.c: New test. * gcc.target/i386/zext-avx512f-1.c: Likewise. * gcc.target/i386/zext-avx512fp16-1.c: Likewise. * gcc.target/i386/zext-sse-1.c: Likewise. * gcc.target/i386/zext-sse-2.c: Likewise. Signed-off-by: H.J. Lu <[email protected]> Diff: --- gcc/config/i386/i386.md | 16 ++ gcc/config/i386/sse.md | 278 ++++++++++++++++++++++ gcc/config/i386/subst.md | 39 +++ gcc/testsuite/gcc.target/i386/zext-avx10-1.c | 139 +++++++++++ gcc/testsuite/gcc.target/i386/zext-avx512f-1.c | 241 +++++++++++++++++++ gcc/testsuite/gcc.target/i386/zext-avx512fp16-1.c | 139 +++++++++++ gcc/testsuite/gcc.target/i386/zext-sse-1.c | 103 ++++++++ gcc/testsuite/gcc.target/i386/zext-sse-2.c | 68 ++++++ 8 files changed, 1023 insertions(+) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 3244bc6240de..f6bfde1f4eda 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -6068,6 +6068,22 @@ (set_attr "amdfam10_decode" "double,double") (set_attr "bdver1_decode" "double,double")]) +(define_insn "*fix_trunc<mode>si_sse_zext" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI + (fix:SI (match_operand:MODEF 1 "nonimmediate_operand" "v,m"))))] + "TARGET_64BIT + && SSE_FLOAT_MODE_P (<MODE>mode) + && (!TARGET_FISTTP || TARGET_SSE_MATH)" + "%vcvtt<ssemodesuffix>2si{l}\t{%1, %k0|%k0, %1}" + [(set_attr "type" "sseicvt") + (set_attr "prefix" "maybe_vex") + (set_attr "prefix_rex" "*") + (set_attr "mode" "<MODE>") + (set_attr "athlon_decode" "double,vector") + (set_attr "amdfam10_decode" "double,double") + (set_attr "bdver1_decode" "double,double")]) + ;; Avoid vector decoded forms of the instruction. (define_peephole2 [(match_scratch:MODEF 2 "x") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 0f35b20006dc..10850189043c 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -8218,6 +8218,20 @@ (set_attr "prefix" "evex") (set_attr "mode" "<MODE>")]) +(define_insn "*avx512fp16_vcvtsh2<sseintconvertsignprefix>si<round_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unspec:SI + [(vec_select:HF + (match_operand:V8HF 1 "register_operand" "v") + (parallel [(const_int 0)]))] + UNSPEC_US_FIX_NOTRUNC)))] + "TARGET_64BIT && TARGET_AVX512FP16" + "vcvtsh2<sseintconvertsignprefix>si\t{<round_zext_op2>%1, %k0|%k0, %1<round_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "prefix" "evex") + (set_attr "mode" "SI")]) + (define_insn "avx512fp16_vcvtsh2<sseintconvertsignprefix>si<rex64namesuffix>_2" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (unspec:SWI48 @@ -8229,6 +8243,18 @@ (set_attr "prefix" "evex") (set_attr "mode" "<MODE>")]) +(define_insn "*avx512fp16_vcvtsh2<sseintconvertsignprefix>si_2_zext" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unspec:SI + [(match_operand:HF 1 "nonimmediate_operand" "vm")] + UNSPEC_US_FIX_NOTRUNC)))] + "TARGET_64BIT && TARGET_AVX512FP16" + "vcvtsh2<sseintconvertsignprefix>si\t{%1, %k0|%k0, %1}" + [(set_attr "type" "sseicvt") + (set_attr "prefix" "evex") + (set_attr "mode" "SI")]) + (define_mode_attr sseicvtsuffix [(SI "l") (DI "q")]) (define_insn "avx512fp16_vcvt<floatsuffix>si2sh<rex64namesuffix><round_name>" @@ -8383,6 +8409,18 @@ (set_attr "prefix" "evex") (set_attr "mode" "<MODE>")]) +(define_insn "*unspec_avx512fp16_fix<vcvtt_uns_suffix>_truncsi2<round_saeonly_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unspec:SI + [(match_operand:V8HF 1 "register_operand" "v")] + UNSPEC_VCVTT_U)))] + "TARGET_64BIT && TARGET_AVX512FP16" + "vcvttsh2<vcvtt_suffix>si\t{<round_saeonly_zext_op2>%1, %k0|%k0, %k1<round_saeonly_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "prefix" "evex") + (set_attr "mode" "SI")]) + (define_insn "avx512fp16_fix<fixunssuffix>_trunc<mode>2<round_saeonly_name>" [(set (match_operand:SWI48 0 "register_operand" "=r") (any_fix:SWI48 @@ -8949,6 +8987,23 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "<MODE>")]) +(define_insn "*sse_cvtss2si<round_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI + (unspec:SI + [(vec_select:SF + (match_operand:V4SF 1 "<round_zext_nimm_scalar_predicate>" "v,<round_zext_constraint2>") + (parallel [(const_int 0)]))] + UNSPEC_FIX_NOTRUNC)))] + "TARGET_64BIT && TARGET_SSE" + "%vcvtss2si{l}\t{<round_zext_op2>%1, %k0|%k0, %k1<round_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "athlon_decode" "double,vector") + (set_attr "bdver1_decode" "double,double") + (set_attr "prefix_rep" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "SI")]) + (define_insn "sse_cvtss2si<rex64namesuffix>_2" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (unspec:SWI48 [(match_operand:SF 1 "nonimmediate_operand" "v,m")] @@ -8963,6 +9018,22 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "<MODE>")]) +(define_insn "*sse_cvtss2si_2_zext" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI + (unspec:SI + [(match_operand:SF 1 "nonimmediate_operand" "v,m")] + UNSPEC_FIX_NOTRUNC)))] + "TARGET_64BIT && TARGET_SSE" + "%vcvtss2si{l}\t{%1, %k0|%k0, %1}" + [(set_attr "type" "sseicvt") + (set_attr "athlon_decode" "double,vector") + (set_attr "amdfam10_decode" "double,double") + (set_attr "bdver1_decode" "double,double") + (set_attr "prefix_rep" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "SI")]) + (define_insn "unspec_sse_cvttss2si<rex64namesuffix><round_saeonly_name>" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (unspec:SWI48 @@ -8978,6 +9049,22 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "<MODE>")]) +(define_insn "*unspec_sse_cvttss2si<round_saeonly_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI + (unspec:SI + [(match_operand:V4SF 1 "<round_saeonly_zext_nimm_scalar_predicate>" "v,<round_saeonly_zext_constraint>")] + UNSPEC_VCVTT)))] + "TARGET_64BIT && TARGET_SSE" + "%vcvttss2si{l}\t{<round_saeonly_zext_op2>%1, %k0|%k0, %k1<round_saeonly_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "athlon_decode" "double,vector") + (set_attr "amdfam10_decode" "double,double") + (set_attr "bdver1_decode" "double,double") + (set_attr "prefix_rep" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "SI")]) + (define_insn "sse_cvttss2si<rex64namesuffix><round_saeonly_name>" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (fix:SWI48 @@ -8994,6 +9081,23 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "<MODE>")]) +(define_insn "*sse_cvttss2si<round_saeonly_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI + (fix:SI + (vec_select:SF + (match_operand:V4SF 1 "<round_saeonly_zext_nimm_scalar_predicate>" "v,<round_saeonly_zext_constraint>") + (parallel [(const_int 0)])))))] + "TARGET_64BIT && TARGET_SSE" + "%vcvttss2si{l}\t{<round_saeonly_zext_op2>%1, %k0|%k0, %k1<round_saeonly_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "athlon_decode" "double,vector") + (set_attr "amdfam10_decode" "double,double") + (set_attr "bdver1_decode" "double,double") + (set_attr "prefix_rep" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "SI")]) + (define_insn "cvtusi2<ssescalarmodesuffix>32<round_name>" [(set (match_operand:VF_128 0 "register_operand" "=v") (vec_merge:VF_128 @@ -9418,6 +9522,20 @@ (set_attr "prefix" "evex") (set_attr "mode" "<MODE>")]) +(define_insn "*avx512f_vcvtss2usi<round_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unspec:SI + [(vec_select:SF + (match_operand:V4SF 1 "<round_zext_nimm_predicate>" "<round_zext_constraint>") + (parallel [(const_int 0)]))] + UNSPEC_UNSIGNED_FIX_NOTRUNC)))] + "TARGET_64BIT && TARGET_AVX512F" + "vcvtss2usi\t{<round_zext_op2>%1, %k0|%k0, %k1<round_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "prefix" "evex") + (set_attr "mode" "SI")]) + (define_insn "unspec_avx512f_vcvttss2usi<rex64namesuffix><round_saeonly_name>" [(set (match_operand:SWI48 0 "register_operand" "=r") (unspec:SWI48 @@ -9429,6 +9547,18 @@ (set_attr "prefix" "evex") (set_attr "mode" "<MODE>")]) +(define_insn "*unspec_avx512f_vcvttss2usi<round_saeonly_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unspec:SI + [(match_operand:V4SF 1 "<round_saeonly_zext_nimm_scalar_predicate>" "<round_saeonly_zext_constraint>")] + UNSPEC_VCVTTU)))] + "TARGET_64BIT && TARGET_AVX512F" + "vcvttss2usi\t{<round_saeonly_zext_op2>%1, %k0|%k0, %k1<round_saeonly_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "prefix" "evex") + (set_attr "mode" "SI")]) + (define_insn "avx512f_vcvttss2usi<rex64namesuffix><round_saeonly_name>" [(set (match_operand:SWI48 0 "register_operand" "=r") (unsigned_fix:SWI48 @@ -9441,6 +9571,19 @@ (set_attr "prefix" "evex") (set_attr "mode" "<MODE>")]) +(define_insn "*avx512f_vcvttss2usi<round_saeonly_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unsigned_fix:SI + (vec_select:SF + (match_operand:V4SF 1 "<round_saeonly_zext_nimm_scalar_predicate>" "<round_saeonly_zext_constraint>") + (parallel [(const_int 0)])))))] + "TARGET_64BIT && TARGET_AVX512F" + "vcvttss2usi\t{<round_saeonly_zext_op2>%1, %k0|%k0, %k1<round_saeonly_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "prefix" "evex") + (set_attr "mode" "SI")]) + (define_insn "avx512f_vcvtsd2usi<rex64namesuffix><round_name>" [(set (match_operand:SWI48 0 "register_operand" "=r") (unspec:SWI48 @@ -9454,6 +9597,20 @@ (set_attr "prefix" "evex") (set_attr "mode" "<MODE>")]) +(define_insn "*avx512f_vcvtsd2usi<round_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unspec:SI + [(vec_select:DF + (match_operand:V2DF 1 "<round_zext_nimm_predicate>" "<round_zext_constraint>") + (parallel [(const_int 0)]))] + UNSPEC_UNSIGNED_FIX_NOTRUNC)))] + "TARGET_64BIT && TARGET_AVX512F" + "vcvtsd2usi\t{<round_zext_op2>%1, %k0|%k0, %q1<round_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "prefix" "evex") + (set_attr "mode" "SI")]) + (define_insn "unspec_avx512f_vcvttsd2usi<rex64namesuffix><round_saeonly_name>" [(set (match_operand:SWI48 0 "register_operand" "=r") (unspec:SWI48 @@ -9465,6 +9622,18 @@ (set_attr "prefix" "evex") (set_attr "mode" "<MODE>")]) +(define_insn "*unspec_avx512f_vcvttsd2usi<round_saeonly_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unspec:SI + [(match_operand:V2DF 1 "<round_saeonly_zext_nimm_scalar_predicate>" "<round_saeonly_zext_constraint>")] + UNSPEC_VCVTTU)))] + "TARGET_64BIT && TARGET_AVX512F" + "vcvttsd2usi\t{<round_saeonly_zext_op2>%1, %k0|%k0, %q1<round_saeonly_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "prefix" "evex") + (set_attr "mode" "SI")]) + (define_insn "avx512f_vcvttsd2usi<rex64namesuffix><round_saeonly_name>" [(set (match_operand:SWI48 0 "register_operand" "=r") (unsigned_fix:SWI48 @@ -9477,6 +9646,19 @@ (set_attr "prefix" "evex") (set_attr "mode" "<MODE>")]) +(define_insn "*avx512f_vcvttsd2usi<round_saeonly_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unsigned_fix:SI + (vec_select:DF + (match_operand:V2DF 1 "<round_saeonly_zext_nimm_scalar_predicate>" "<round_saeonly_zext_constraint>") + (parallel [(const_int 0)])))))] + "TARGET_64BIT && TARGET_AVX512F" + "vcvttsd2usi\t{<round_saeonly_zext_op2>%1, %k0|%k0, %q1<round_saeonly_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "prefix" "evex") + (set_attr "mode" "SI")]) + (define_insn "sse2_cvtsd2si<rex64namesuffix><round_name>" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (unspec:SWI48 @@ -9494,6 +9676,24 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "<MODE>")]) +(define_insn "*sse2_cvtsd2si<round_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI + (unspec:SI + [(vec_select:DF + (match_operand:V2DF 1 "<round_zext_nimm_scalar_predicate>" "v,<round_zext_constraint2>") + (parallel [(const_int 0)]))] + UNSPEC_FIX_NOTRUNC)))] + "TARGET_64BIT && TARGET_SSE2" + "%vcvtsd2si{l}\t{<round_zext_op2>%1, %k0|%k0, %q1<round_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "athlon_decode" "double,vector") + (set_attr "bdver1_decode" "double,double") + (set_attr "btver2_decode" "double,double") + (set_attr "prefix_rep" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "SI")]) + (define_insn "sse2_cvtsd2si<rex64namesuffix>_2" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (unspec:SWI48 [(match_operand:DF 1 "nonimmediate_operand" "v,m")] @@ -9508,6 +9708,21 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "<MODE>")]) +(define_insn "*sse2_cvtsd2si_2_zext" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI + (unspec:SI [(match_operand:DF 1 "nonimmediate_operand" "v,m")] + UNSPEC_FIX_NOTRUNC)))] + "TARGET_64BIT && TARGET_SSE2" + "%vcvtsd2si{l}\t{%1, %k0|%k0, %q1}" + [(set_attr "type" "sseicvt") + (set_attr "athlon_decode" "double,vector") + (set_attr "amdfam10_decode" "double,double") + (set_attr "bdver1_decode" "double,double") + (set_attr "prefix_rep" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "SI")]) + (define_insn "unspec_sse2_cvttsd2si<rex64namesuffix><round_saeonly_name>" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (unspec:SWI48 @@ -9524,6 +9739,23 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "<MODE>")]) +(define_insn "*unspec_sse2_cvttsd2si<round_saeonly_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI + (unspec:SI + [(match_operand:V2DF 1 "<round_saeonly_zext_nimm_scalar_predicate>" "v,<round_saeonly_zext_constraint2>")] + UNSPEC_VCVTT)))] + "TARGET_64BIT && TARGET_SSE2" + "%vcvttsd2si{l}\t{<round_saeonly_zext_op2>%1, %k0|%k0, %q1<round_saeonly_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "athlon_decode" "double,vector") + (set_attr "amdfam10_decode" "double,double") + (set_attr "bdver1_decode" "double,double") + (set_attr "btver2_decode" "double,double") + (set_attr "prefix_rep" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "SI")]) + (define_insn "sse2_cvttsd2si<rex64namesuffix><round_saeonly_name>" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (fix:SWI48 @@ -9541,6 +9773,24 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "<MODE>")]) +(define_insn "*sse2_cvttsd2si<round_saeonly_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI + (fix:SI + (vec_select:DF + (match_operand:V2DF 1 "<round_saeonly_zext_nimm_scalar_predicate>" "v,<round_saeonly_zext_constraint2>") + (parallel [(const_int 0)])))))] + "TARGET_64BIT && TARGET_SSE2" + "%vcvttsd2si{l}\t{<round_saeonly_zext_op2>%1, %k0|%k0, %q1<round_saeonly_zext_op2>}" + [(set_attr "type" "sseicvt") + (set_attr "athlon_decode" "double,vector") + (set_attr "amdfam10_decode" "double,double") + (set_attr "bdver1_decode" "double,double") + (set_attr "btver2_decode" "double,double") + (set_attr "prefix_rep" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "SI")]) + ;; For float<si2dfmode><mode>2 insn pattern (define_mode_attr si2dfmode [(V8DF "V8SI") (V4DF "V4SI")]) @@ -33691,6 +33941,20 @@ (set_attr "prefix" "evex") (set_attr "mode" "<MODE>")]) +(define_insn "*avx10_2_vcvttsd2<sat_cvt_sign_prefix>sissi<round_saeonly_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unspec:SI + [(vec_select:DF + (match_operand:V2DF 1 "<round_saeonly_zext_nimm_scalar_predicate>" "<round_saeonly_zext_constraint>") + (parallel [(const_int 0)]))] + UNSPEC_SAT_CVT_DS_SIGN_ITER)))] + "TARGET_64BIT && TARGET_AVX10_2" + "vcvttsd2<sat_cvt_sign_prefix>sis\t{<round_saeonly_zext_op2>%1, %k0|%k0, %q1<round_saeonly_zext_op2>}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "SI")]) + (define_insn "avx10_2_vcvttss2<sat_cvt_sign_prefix>sis<mode><round_saeonly_name>" [(set (match_operand:SWI48 0 "register_operand" "=r") (unspec:SWI48 @@ -33704,6 +33968,20 @@ (set_attr "prefix" "evex") (set_attr "mode" "<MODE>")]) +(define_insn "*avx10_2_vcvttss2<sat_cvt_sign_prefix>sissi<round_saeonly_zext_name>" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unspec:SI + [(vec_select:SF + (match_operand:V4SF 1 "<round_saeonly_zext_nimm_scalar_predicate>" "<round_saeonly_zext_constraint>") + (parallel [(const_int 0)]))] + UNSPEC_SAT_CVT_DS_SIGN_ITER)))] + "TARGET_64BIT && TARGET_AVX10_2" + "vcvttss2<sat_cvt_sign_prefix>sis\t{<round_saeonly_zext_op2>%1, %k0|%k0, %k1<round_saeonly_zext_op2>}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "SI")]) + (define_insn "avx10_2_minmaxbf16_<mode><mask_name>" [(set (match_operand:VBF 0 "register_operand" "=v") (unspec:VBF diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index 454f0989f07c..511fd6ad5c24 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -482,3 +482,42 @@ (match_dup 1) (match_operand:SUBST_V 2 "const0_operand") (match_operand:<avx512fmaskhalfmode> 3 "register_operand" "Yk")))]) + +(define_subst_attr "round_zext_name" "round_zext" "_zext" "_round_zext") +(define_subst_attr "round_zext_constraint" "round_zext" "vm" "v") +(define_subst_attr "round_zext_constraint2" "round_zext" "m" "v") +(define_subst_attr "round_zext_nimm_predicate" "round_zext" "vector_operand" "register_operand") +(define_subst_attr "round_zext_nimm_scalar_predicate" "round_zext" "nonimmediate_operand" "register_operand") +(define_subst_attr "round_zext_op2" "round_zext" "" "%R2") + +(define_subst "round_zext" + [(set (match_operand:DI 0) + (zero_extend:DI + (match_operand:SI 1)))] + "TARGET_64BIT && TARGET_AVX512F" + [(set (match_dup 0) + (zero_extend:DI + (unspec:SI + [(match_dup 1) + (match_operand:SI 2 "const_4_or_8_to_11_operand")] + UNSPEC_EMBEDDED_ROUNDING))) +]) + +(define_subst_attr "round_saeonly_zext_name" "round_saeonly_zext" "_zext" "_round_zext") +(define_subst_attr "round_saeonly_zext_constraint" "round_saeonly_zext" "vm" "v") +(define_subst_attr "round_saeonly_zext_constraint2" "round_saeonly_zext" "m" "v") +(define_subst_attr "round_saeonly_zext_nimm_scalar_predicate" "round_saeonly_zext" "nonimmediate_operand" "register_operand") +(define_subst_attr "round_saeonly_zext_op2" "round_saeonly_zext" "" "%r2") + +(define_subst "round_saeonly_zext" + [(set (match_operand:DI 0) + (zero_extend:DI + (match_operand:SI 1)))] + "TARGET_64BIT && TARGET_AVX512F" + [(set (match_dup 0) + (zero_extend:DI + (unspec:SI + [(match_dup 1) + (match_operand:SI 2 "const48_operand")] + UNSPEC_EMBEDDED_ROUNDING))) +]) diff --git a/gcc/testsuite/gcc.target/i386/zext-avx10-1.c b/gcc/testsuite/gcc.target/i386/zext-avx10-1.c new file mode 100644 index 000000000000..66f28125fffd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/zext-avx10-1.c @@ -0,0 +1,139 @@ +/* PR target/126231 */ +/* { dg-do compile { target { *-*-linux* && lp64 } } } */ +/* { dg-options "-O2 -march=x86-64-v4 -mavx10.2" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +#include <x86intrin.h> + +/* +**func1: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttss2usis %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func1 (__m128 x) +{ + return _mm_cvtts_ss_epu32 (x); +} + +/* +**func2: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttss2usis \{sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func2 (__m128 x) +{ + return _mm_cvtts_roundss_epu32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + +/* +**func3: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttss2sis %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func3 (__m128 x) +{ + return (unsigned int) _mm_cvtts_ss_epi32 (x); +} + +/* +**func4: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttss2sis \{sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func4 (__m128 x) +{ + return (unsigned int) _mm_cvtts_roundss_epi32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + +/* +**func5: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttsd2usis %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func5 (__m128d x) +{ + return _mm_cvtts_sd_epu32 (x); +} + +/* +**func6: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttsd2usis \{sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func6 (__m128d x) +{ + return _mm_cvtts_roundsd_epu32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + +/* +**func7: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttsd2sis %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func7 (__m128d x) +{ + return (unsigned int) _mm_cvtts_sd_epi32 (x); +} + +/* +**func8: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttsd2sis \{sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func8 (__m128d x) +{ + return (unsigned int) _mm_cvtts_roundsd_epi32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/zext-avx512f-1.c b/gcc/testsuite/gcc.target/i386/zext-avx512f-1.c new file mode 100644 index 000000000000..deae5e487e88 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/zext-avx512f-1.c @@ -0,0 +1,241 @@ +/* PR target/126231 */ +/* { dg-do compile { target { *-*-linux* && lp64 } } } */ +/* { dg-options "-O2 -march=x86-64-v4" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +#include <x86intrin.h> + +/* +**func1: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttss2sil %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func1 (__m128 x) +{ + return (unsigned int) _mm_cvttss_i32 (x); +} + +/* +**func2: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttss2sil \{sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func2 (__m128 x) +{ + return (unsigned int) _mm_cvtt_roundss_i32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + +/* +**func3: +**.LFB[0-9]+: +** .cfi_startproc +** vcvtss2usi %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func3 (__m128 x) +{ + return (unsigned int) _mm_cvtss_u32 (x); +} + +/* +**func4: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttss2usi %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func4 (__m128 x) +{ + return (unsigned int) _mm_cvttss_u32 (x); +} + +/* +**func5: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttss2usi \{sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func5 (__m128 x) +{ + return (unsigned int) _mm_cvtt_roundss_u32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + +/* +**func6: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttsd2usi %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func6 (__m128d x) +{ + return (unsigned int) _mm_cvttsd_u32 (x); +} + +/* +**func7: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttsd2usi \{sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func7 (__m128d x) +{ + return (unsigned int) _mm_cvtt_roundsd_u32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + +/* +**func8: +**.LFB[0-9]+: +** .cfi_startproc +** vcvtsd2usi %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func8 (__m128d x) +{ + return (unsigned int) _mm_cvtsd_u32 (x); +} + +/* +**func9: +**.LFB[0-9]+: +** .cfi_startproc +** vcvtsd2usi \{rn-sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func9 (__m128d x) +{ + return (unsigned int) _mm_cvt_roundsd_u32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + + +/* +**func10: +**.LFB[0-9]+: +** .cfi_startproc +** vcvtsd2sil \{rn-sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func10 (__m128d x) +{ + return (unsigned int) _mm_cvt_roundsd_si32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + +/* +**func11: +**.LFB[0-9]+: +** .cfi_startproc +** vcvtsd2sil \{rn-sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func11 (__m128d x) +{ + return (unsigned int) _mm_cvt_roundsd_i32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + +/* +**func12: +**.LFB[0-9]+: +** .cfi_startproc +** vcvtss2usi \{rn-sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func12 (__m128 x) +{ + return (unsigned int) _mm_cvt_roundss_u32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + +/* +**func13: +**.LFB[0-9]+: +** .cfi_startproc +** vcvtss2sil \{rn-sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func13 (__m128 x) +{ + return (unsigned int) _mm_cvt_roundss_si32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + +/* +**func14: +**.LFB[0-9]+: +** .cfi_startproc +** vcvtss2sil \{rn-sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func14 (__m128 x) +{ + return (unsigned int) _mm_cvt_roundss_i32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/zext-avx512fp16-1.c b/gcc/testsuite/gcc.target/i386/zext-avx512fp16-1.c new file mode 100644 index 000000000000..a4e50c4f6d8e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/zext-avx512fp16-1.c @@ -0,0 +1,139 @@ +/* PR target/126231 */ +/* { dg-do compile { target { *-*-linux* && lp64 } } } */ +/* { dg-options "-O2 -march=x86-64-v4 -mavx512fp16" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +#include <x86intrin.h> + +/* +**func1: +**.LFB[0-9]+: +** .cfi_startproc +** vcvtsh2si %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func1 (__m128h x) +{ + return (unsigned int) _mm_cvtsh_i32 (x); +} + +/* +**func2: +**.LFB[0-9]+: +** .cfi_startproc +** vcvtsh2usi %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func2 (__m128h x) +{ + return _mm_cvtsh_u32 (x); +} + +/* +**func3: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttsh2si %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func3 (__m128h x) +{ + return (unsigned int) _mm_cvttsh_i32 (x); +} + +/* +**func4: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttsh2usi %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func4 (__m128h x) +{ + return _mm_cvttsh_u32 (x); +} + +/* +**func5: +**.LFB[0-9]+: +** .cfi_startproc +** vcvtsh2usi \{rn-sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func5 (__m128h x) +{ + return _mm_cvt_roundsh_u32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + +/* +**func6: +**.LFB[0-9]+: +** .cfi_startproc +** vcvtsh2si \{rn-sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func6 (__m128h x) +{ + return (unsigned int) _mm_cvt_roundsh_i32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + +/* +**func7: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttsh2usi \{sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func7 (__m128h x) +{ + return _mm_cvtt_roundsh_u32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} + +/* +**func8: +**.LFB[0-9]+: +** .cfi_startproc +** vcvttsh2si \{sae\}, %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func8 (__m128h x) +{ + return (unsigned int) _mm_cvtt_roundsh_i32 + (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/zext-sse-1.c b/gcc/testsuite/gcc.target/i386/zext-sse-1.c new file mode 100644 index 000000000000..0965c89ddf42 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/zext-sse-1.c @@ -0,0 +1,103 @@ +/* PR target/126231 */ +/* { dg-do compile { target { *-*-linux* && lp64 } } } */ +/* { dg-options "-O2 -march=x86-64" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +#include <emmintrin.h> + +/* +**func1: +**.LFB[0-9]+: +** .cfi_startproc +** cvttss2sil %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func1 (float x) +{ + return (unsigned int) x; +} + +/* +**func2: +**.LFB[0-9]+: +** .cfi_startproc +** cvttsd2sil %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func2 (double x) +{ + return (unsigned int) x; +} + +/* +**func3: +**.LFB[0-9]+: +** .cfi_startproc +** cvttss2sil %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func3 (__m128 x) +{ + return (unsigned int) _mm_cvttss_si32 (x); +} + +/* +**func4: +**.LFB[0-9]+: +** .cfi_startproc +** cvtss2sil %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func4 (__m128 x) +{ + return (unsigned int) _mm_cvtss_si32 (x); +} + +/* +**func5: +**.LFB[0-9]+: +** .cfi_startproc +** cvttsd2sil %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func5 (__m128d x) +{ + return (unsigned int) _mm_cvttsd_si32 (x); +} + +/* +**func6: +**.LFB[0-9]+: +** .cfi_startproc +** cvtsd2sil %xmm0, %eax +** ret +** .cfi_endproc +**... +*/ + +unsigned long long +func6 (__m128d x) +{ + return (unsigned int) _mm_cvtsd_si32 (x); +} diff --git a/gcc/testsuite/gcc.target/i386/zext-sse-2.c b/gcc/testsuite/gcc.target/i386/zext-sse-2.c new file mode 100644 index 000000000000..7d917cfd5de9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/zext-sse-2.c @@ -0,0 +1,68 @@ +/* PR target/126231 */ +/* { dg-do compile { target { *-*-linux* && lp64 } } } */ +/* { dg-options "-O2 -march=x86-64" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +struct foo +{ + int i; + int j; + int k; +}; + +struct bar1 +{ + double x; + double y; + double z; +}; + +struct bar2 +{ + float x; + float y; + float z; +}; + +/* +**func1: +**.LFB[0-9]+: +** .cfi_startproc +** cvttsd2sil 16\(%rdi\), %ecx +** movupd \(%rdi\), %xmm1 +** cvttpd2dq %xmm1, %xmm0 +** movq %xmm0, %rax +** movq %rcx, %rdx +** ret +** .cfi_endproc +**... +*/ + +struct foo +func1 (struct bar1 *x) +{ + return (struct foo) { x->x, x->y, x->z }; +} + +/* +**func2: +**.LFB[0-9]+: +** .cfi_startproc +** cvttss2sil 8\(%rdi\), %eax +** movq \(%rdi\), %xmm0 +** cvttps2dq %xmm0, %xmm0 +** movq %xmm0, %rsi +** movq %rax, %rdi +** movq %rsi, %rax +** movq %rdi, %rdx +** ret +** .cfi_endproc +**... +*/ + +struct foo +func2 (struct bar2 *x) +{ + return (struct foo) { x->x, x->y, x->z }; +}
