https://gcc.gnu.org/g:80aff0f9107236f18b78572859926a8f128fbc7e
commit 80aff0f9107236f18b78572859926a8f128fbc7e Author: Surya Kumari Jangala <[email protected]> Date: Wed Jul 15 07:13:11 2026 -0500 rs6000: Add TDOmode reload patterns for DMR registers Add define_insn_and_split patterns for reloading TDOmode values between Dense Math Registers (DMRs) and memory when TARGET_DMF is enabled. 2026-07-15 Surya Kumari Jangala <[email protected]> Peter Bergner <[email protected]> gcc: * config/rs6000/mma.md (UNSPEC_DMR_RELOAD_FROM_MEMORY): New unspec. (UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise. (reload_tdo_load): New define_insn_and_split. (reload_tdo_store): Likewise. * config/rs6000/rs6000.cc (rs6000_init_hard_regno_mode_ok): Set reload_load and reload_store for TDOmode when TARGET_DMF. Diff: --- gcc/config/rs6000/mma.md | 70 +++++++++++++++++++++++++++++++++++++++++++++ gcc/config/rs6000/rs6000.cc | 6 ++++ 2 files changed, 76 insertions(+) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 2b0736d86a64..6cd4f12bb336 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -94,6 +94,8 @@ UNSPEC_DMF_INSERT512 UNSPEC_DMF_EXTRACT512 UNSPEC_DMF_INSERT1024 + UNSPEC_DMR_RELOAD_FROM_MEMORY + UNSPEC_DMR_RELOAD_TO_MEMORY ]) (define_c_enum "unspecv" @@ -535,6 +537,74 @@ gcc_unreachable (); }) + +(define_insn_and_split "reload_tdo_load" + [(set (match_operand:TDO 0 "dmr_register_operand" "=wD") + (unspec:TDO [(match_operand:TDO 1 "memory_operand" "m")] + UNSPEC_DMR_RELOAD_FROM_MEMORY)) + (clobber (match_operand:OO 2 "vsx_register_operand" "=wa")) + (clobber (match_operand:OO 3 "vsx_register_operand" "=wa")) + (clobber (match_operand:OO 4 "vsx_register_operand" "=wa")) + (clobber (match_operand:OO 5 "vsx_register_operand" "=wa"))] + "TARGET_DMF" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + rtx pair0 = operands[2]; + rtx pair1 = operands[3]; + rtx pair2 = operands[4]; + rtx pair3 = operands[5]; + + if (BYTES_BIG_ENDIAN) + { + emit_move_insn (pair0, adjust_address (src, OOmode, 0)); + emit_move_insn (pair1, adjust_address (src, OOmode, 32)); + emit_move_insn (pair2, adjust_address (src, OOmode, 64)); + emit_move_insn (pair3, adjust_address (src, OOmode, 96)); + } + else + { + emit_move_insn (pair3, adjust_address (src, OOmode, 0)); + emit_move_insn (pair2, adjust_address (src, OOmode, 32)); + emit_move_insn (pair1, adjust_address (src, OOmode, 64)); + emit_move_insn (pair0, adjust_address (src, OOmode, 96)); + } + emit_insn (gen_dm_insert1024 (dest, pair0, pair1, pair2, pair3)); + DONE; +} + [(set_attr "max_prefixed_insns" "4")]) + + +;; Reload dense math register to memory +(define_insn_and_split "reload_tdo_store" + [(set (match_operand:TDO 0 "memory_operand" "=m") + (unspec:TDO [(match_operand:TDO 1 "dmr_register_operand" "wD")] + UNSPEC_DMR_RELOAD_TO_MEMORY)) + (clobber (match_operand:XO 2 "vsx_register_operand" "=wa"))] + "TARGET_DMF" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + rtx tmp_vsx_512 = operands[2]; + rtx high_mem = adjust_address (dest, XOmode, BYTES_BIG_ENDIAN ? 0 : 64); + rtx low_mem = adjust_address (dest, XOmode, BYTES_BIG_ENDIAN ? 64 : 0); + + emit_insn (gen_dm_extract512 (tmp_vsx_512, src, const0_rtx)); + emit_move_insn (high_mem, tmp_vsx_512); + + emit_insn (gen_dm_extract512 (tmp_vsx_512, src, const1_rtx)); + emit_move_insn (low_mem, tmp_vsx_512); + DONE; +} + [(set_attr "max_prefixed_insns" "4")]) + + (define_expand "mma_assemble_acc" [(match_operand:XO 0 "accumulator_operand") (match_operand:V16QI 1 "mma_assemble_input_operand") diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 3379a3a0e1d4..caef7b991589 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3218,6 +3218,12 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) } } + if (TARGET_DMF) + { + reg_addr[TDOmode].reload_load = CODE_FOR_reload_tdo_load; + reg_addr[TDOmode].reload_store = CODE_FOR_reload_tdo_store; + } + /* Precalculate HARD_REGNO_NREGS. */ for (r = 0; HARD_REGISTER_NUM_P (r); ++r) for (m = 0; m < NUM_MACHINE_MODES; ++m)
