https://gcc.gnu.org/g:a4cb95eacb360531a7ff843f1a833d34cecdb6ba
commit r17-2637-ga4cb95eacb360531a7ff843f1a833d34cecdb6ba Author: Pan Li <[email protected]> Date: Wed Jul 22 09:30:05 2026 +0800 RISC-V: Allow RVV register overlap for vfwcvt.rtz.x[u].f.v Like v[sz]ext.vf8, allow the rvv register overlap for vfwcvt.x[u].f.v. gcc/ChangeLog: * config/riscv/vector.md: Leverage Wvr constraint. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/config/riscv/vector.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 44dfe003f31a..32c0036ffa43 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7848,19 +7848,19 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) (define_insn "@pred_widen_<fix_cvt><mode>" - [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr") + [(set (match_operand:VWCONVERTI 0 "register_operand" "=vr, vr, vd, vd") (if_then_else:VWCONVERTI (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rvl, rvl") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "Wc1,Wc1, vm, vm") + (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix:VWCONVERTI - (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")) - (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] + (match_operand:<VNCONVERT> 3 "register_operand" "Wvr,Wvr,Wvr,Wvr")) + (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftoi")
