https://gcc.gnu.org/g:b3ef2a69325c1c5d9a05df8ac48fc256f8862480
commit r17-3210-gb3ef2a69325c1c5d9a05df8ac48fc256f8862480 Author: Jin Ma <[email protected]> Date: Sat Jul 18 17:41:01 2026 +0800 RISC-V: Widen fusion pair bitmask to unsigned HOST_WIDE_INT The riscv_fusion_pairs enum and the fusible_ops tune field use unsigned int, leaving only 18 bits for new fusion types. Widen them to unsigned HOST_WIDE_INT so that future CPUs can define more than 32 fusion pairs without overflow. gcc/ChangeLog: * config/riscv/riscv-protos.h (enum riscv_fusion_pairs): Use HOST_WIDE_INT_1U for bit masks. (riscv_get_fusible_ops): Return unsigned HOST_WIDE_INT. * config/riscv/riscv.cc (struct riscv_tune_param): Change fusible_ops to unsigned HOST_WIDE_INT. (riscv_get_fusible_ops): Likewise. Signed-off-by: Jin Ma <[email protected]> Diff: --- gcc/config/riscv/riscv-protos.h | 30 +++++++++++++++--------------- gcc/config/riscv/riscv.cc | 4 ++-- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 3843110ab6c2..f23aeacf895e 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -853,25 +853,25 @@ extern bool riscv_expand_strlen (rtx, rtx, rtx, rtx); enum riscv_fusion_pairs { RISCV_FUSE_NOTHING = 0, - RISCV_FUSE_ZEXTW = (1 << 0), - RISCV_FUSE_ZEXTH = (1 << 1), - RISCV_FUSE_ZEXTWS = (1 << 2), - RISCV_FUSE_LDINDEXED = (1 << 3), - RISCV_FUSE_LUI_ADDI = (1 << 4), - RISCV_FUSE_AUIPC_ADDI = (1 << 5), - RISCV_FUSE_LUI_LD = (1 << 6), - RISCV_FUSE_AUIPC_LD = (1 << 7), - RISCV_FUSE_LDPREINCREMENT = (1 << 8), - RISCV_FUSE_ALIGNED_STD = (1 << 9), - RISCV_FUSE_CACHE_ALIGNED_STD = (1 << 10), - RISCV_FUSE_BFEXT = (1 << 11), - RISCV_FUSE_EXPANDED_LD = (1 << 12), - RISCV_FUSE_B_ALUI = (1 << 13), + RISCV_FUSE_ZEXTW = HOST_WIDE_INT_1U << 0, + RISCV_FUSE_ZEXTH = HOST_WIDE_INT_1U << 1, + RISCV_FUSE_ZEXTWS = HOST_WIDE_INT_1U << 2, + RISCV_FUSE_LDINDEXED = HOST_WIDE_INT_1U << 3, + RISCV_FUSE_LUI_ADDI = HOST_WIDE_INT_1U << 4, + RISCV_FUSE_AUIPC_ADDI = HOST_WIDE_INT_1U << 5, + RISCV_FUSE_LUI_LD = HOST_WIDE_INT_1U << 6, + RISCV_FUSE_AUIPC_LD = HOST_WIDE_INT_1U << 7, + RISCV_FUSE_LDPREINCREMENT = HOST_WIDE_INT_1U << 8, + RISCV_FUSE_ALIGNED_STD = HOST_WIDE_INT_1U << 9, + RISCV_FUSE_CACHE_ALIGNED_STD = HOST_WIDE_INT_1U << 10, + RISCV_FUSE_BFEXT = HOST_WIDE_INT_1U << 11, + RISCV_FUSE_EXPANDED_LD = HOST_WIDE_INT_1U << 12, + RISCV_FUSE_B_ALUI = HOST_WIDE_INT_1U << 13, }; extern bool riscv_macro_fusion_p (void); extern bool riscv_macro_fusion_pair_p (rtx_insn *, rtx_insn *); -extern unsigned int riscv_get_fusible_ops (void); +extern unsigned HOST_WIDE_INT riscv_get_fusible_ops (void); /* Routines implemented in thead.cc. */ extern bool extract_base_offset_in_addr (rtx, rtx *, rtx *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 6593d00a7e64..f79b55a0c705 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -294,7 +294,7 @@ struct riscv_tune_param bool overlap_op_by_pieces; bool use_zero_stride_load; bool speculative_sched_vsetvl; - unsigned int fusible_ops; + unsigned HOST_WIDE_INT fusible_ops; const struct cpu_vector_cost *vec_costs; const char *function_align; const char *jump_align; @@ -11636,7 +11636,7 @@ riscv_sched_reorder (FILE *, int, rtx_insn **ready, int *nreadyp, int) /* Return the set of fusible operations for the current tune. */ -unsigned int +unsigned HOST_WIDE_INT riscv_get_fusible_ops (void) { return tune_param->fusible_ops;
