https://gcc.gnu.org/g:81d25063773b48a163b0198aa5ed4a5468142e05
commit r17-4170-g81d25063773b48a163b0198aa5ed4a5468142e05 Author: Robin Dapp <[email protected]> Date: Mon Aug 31 14:42:18 2026 +0200 aarch64: Set REGMODE_NATURAL_SIZE for advsimd vectors. Similar to the riscv changes, this patch adjusts aarch64's REGMODE_NATURAL_SIZE so it returns the size of one vectors. Subsequently, subregs of vectors smaller than a vector are invalid. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_regmode_natural_size): Set REGMODE_NATURAL_SIZE to the size of one vector. Diff: --- gcc/config/aarch64/aarch64.cc | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index ccb4f5fbb10d..f9d906f449f2 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -2996,20 +2996,19 @@ aarch64_regmode_natural_size (machine_mode mode) /* The natural size for SVE data modes is one SVE data vector, and similarly for predicates. We can't independently modify anything smaller than that. */ - /* ??? For now, only do this for variable-width SVE registers. - Doing it for constant-sized registers breaks lower-subreg.cc. */ - /* ??? And once that's fixed, we should probably have similar - code for Advanced SIMD. */ - if (!aarch64_sve_vg.is_constant ()) - { - /* REGMODE_NATURAL_SIZE influences general subreg validity rules, - so we need to handle memory-only modes as well. */ + if (VECTOR_MODE_P (mode)) + { unsigned int vec_flags = aarch64_classify_vector_memory_mode (mode); if (vec_flags & VEC_SVE_PRED) return BYTES_PER_SVE_PRED; if (vec_flags & VEC_SVE_DATA) return BYTES_PER_SVE_VECTOR; + if (vec_flags & VEC_ADVSIMD) + return MAX (exact_div (GET_MODE_SIZE (mode), + aarch64_ldn_stn_vectors (mode)).to_constant (), + UNITS_PER_WORD); } + return UNITS_PER_WORD; }
