https://gcc.gnu.org/g:83c53762544f1f7db2b0840cff6a957e7ea47a14
commit r17-4184-g83c53762544f1f7db2b0840cff6a957e7ea47a14 Author: Pan Li <[email protected]> Date: Thu Sep 10 10:02:09 2026 +0800 RISC-V: Add test cases for widening insn ICE [PR target/127269] Add the test cases for the ICE of the widening insn when the dest and the src have the same number of registers. PR target/127269 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr127269-1.c: New test. * gcc.target/riscv/rvv/base/pr127269-2.c: New test. * gcc.target/riscv/rvv/base/pr127269-3.c: New test. * gcc.target/riscv/rvv/base/pr127269-4.c: New test. * gcc.target/riscv/rvv/base/pr127269-5.c: New test. * gcc.target/riscv/rvv/base/pr127269-6.c: New test. * gcc.target/riscv/rvv/base/pr127269-7.c: New test. * gcc.target/riscv/rvv/base/pr127269-8.c: New test. * gcc.target/riscv/rvv/base/pr127269-9.c: New test. * gcc.target/riscv/rvv/base/pr127269-10.c: New test. * gcc.target/riscv/rvv/base/pr127269-11.c: New test. * gcc.target/riscv/rvv/base/pr127269-12.c: New test. * gcc.target/riscv/rvv/base/pr127269-13.c: New test. * gcc.target/riscv/rvv/base/pr127269-14.c: New test. * gcc.target/riscv/rvv/base/pr127269-15.c: New test. * gcc.target/riscv/rvv/base/pr127269-16.c: New test. * gcc.target/riscv/rvv/base/pr127269-17.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-1.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-10.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-11.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-12.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-13.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-14.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-15.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-16.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-17.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-2.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-3.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-4.c | 17 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-5.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-6.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-7.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-8.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-9.c | 16 ++++++++++++++++ 17 files changed, 273 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-1.c new file mode 100644 index 000000000000..5b237dd5c980 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vint32m2_t +test (vint16m2_t a, size_t vl) +{ + vint16m1_t b = __riscv_vget_v_i16m2_i16m1 (a, 0); + return __riscv_vwmul_vv_i32m2 (b, b, vl); +} + +/* { dg-final { scan-assembler-times {vwmul\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-10.c new file mode 100644 index 000000000000..d9a437410de5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-10.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vint32m2_t +test (vint16m2_t a, size_t vl) +{ + vint16m1_t b = __riscv_vget_v_i16m2_i16m1 (a, 0); + return __riscv_vwcvt_x_x_v_i32m2 (b, vl); +} + +/* { dg-final { scan-assembler-times {vwcvt\.x\.x\.v} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-11.c new file mode 100644 index 000000000000..5550b0aadee1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-11.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vint64m4_t +test (vint64m4_t a, vint32m4_t b, size_t vl) +{ + vint32m2_t c = __riscv_vget_v_i32m4_i32m2 (b, 1); + return __riscv_vwadd_wv_i64m4 (a, c, vl); +} + +/* { dg-final { scan-assembler-times {vwadd\.wv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-12.c new file mode 100644 index 000000000000..e9490c162fdf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-12.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vfloat64m2_t +test (vfloat32m2_t a, size_t vl) +{ + vfloat32m1_t b = __riscv_vget_v_f32m2_f32m1 (a, 1); + return __riscv_vfwcvt_f_f_v_f64m2 (b, vl); +} + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-13.c new file mode 100644 index 000000000000..175cf951812c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-13.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vfloat32m4_t +test (vfloat16m4_t a, size_t vl) +{ + vfloat16m2_t b = __riscv_vget_v_f16m4_f16m2 (a, 1); + return __riscv_vfwcvt_f_f_v_f32m4 (b, vl); +} + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-14.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-14.c new file mode 100644 index 000000000000..693646ff44c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-14.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vint32m2_t +test (vint16m2_t a, size_t vl) +{ + vint16m1_t b = __riscv_vlmul_trunc_v_i16m2_i16m1 (a); + return __riscv_vwmul_vv_i32m2 (b, b, vl); +} + +/* { dg-final { scan-assembler-times {vwmul\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-15.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-15.c new file mode 100644 index 000000000000..076522c6e1ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-15.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vfloat32m4_t +test (vint16m4_t a, size_t vl) +{ + vint16m2_t b = __riscv_vget_v_i16m4_i16m2 (a, 1); + return __riscv_vfwcvt_f_x_v_f32m4 (b, vl); +} + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-16.c new file mode 100644 index 000000000000..d38da7922b6e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-16.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vuint32m2_t +test (vfloat16m2_t a, size_t vl) +{ + vfloat16m1_t b = __riscv_vget_v_f16m2_f16m1 (a, 1); + return __riscv_vfwcvt_rtz_xu_f_v_u32m2 (b, vl); +} + +/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.xu\.f\.v} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-17.c new file mode 100644 index 000000000000..ca44b08763bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-17.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vint32m2_t +test (vint16m2_t a, size_t vl) +{ + vint16m1_t b = __riscv_vget_v_i16m2_i16m1 (a, 0); + return __riscv_vwmul_vv_i32m2 (b, b, vl); +} + +/* { dg-final { scan-assembler-times {vwmul\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-2.c new file mode 100644 index 000000000000..fed063611595 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vint32m2_t +test (vint16m2_t a, size_t vl) +{ + vint16m1_t b = __riscv_vget_v_i16m2_i16m1 (a, 1); + return __riscv_vwmul_vv_i32m2 (b, b, vl); +} + +/* { dg-final { scan-assembler-times {vwmul\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-3.c new file mode 100644 index 000000000000..7bd227449a3a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-3.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vint32m4_t +test (vint16m4_t a, size_t vl) +{ + vint16m2_t b = __riscv_vget_v_i16m4_i16m2 (a, 0); + return __riscv_vwadd_vv_i32m4 (b, b, vl); +} + +/* { dg-final { scan-assembler-times {vwadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-4.c new file mode 100644 index 000000000000..00834e8f5df8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vint32m8_t +test (vint16m8_t a, size_t vl) +{ + vint16m4_t b = __riscv_vget_v_i16m8_i16m4 (a, 0); + vint16m4_t c = __riscv_vget_v_i16m8_i16m4 (a, 1); + return __riscv_vwsub_vv_i32m8 (b, c, vl); +} + +/* { dg-final { scan-assembler-times {vwsub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-5.c new file mode 100644 index 000000000000..ddd6c8b02828 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-5.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vuint32m2_t +test (vuint16m2_t a, size_t vl) +{ + vuint16m1_t b = __riscv_vget_v_u16m2_u16m1 (a, 1); + return __riscv_vwmulu_vv_u32m2 (b, b, vl); +} + +/* { dg-final { scan-assembler-times {vwmulu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-6.c new file mode 100644 index 000000000000..301fe5d17192 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-6.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vint16m2_t +test (vint8m2_t a, size_t vl) +{ + vint8m1_t b = __riscv_vget_v_i8m2_i8m1 (a, 0); + return __riscv_vsext_vf2_i16m2 (b, vl); +} + +/* { dg-final { scan-assembler-times {vsext\.vf2} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-7.c new file mode 100644 index 000000000000..ae87bc783213 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-7.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vuint32m4_t +test (vuint8m4_t a, size_t vl) +{ + vuint8m1_t b = __riscv_vget_v_u8m4_u8m1 (a, 2); + return __riscv_vzext_vf4_u32m4 (b, vl); +} + +/* { dg-final { scan-assembler-times {vzext\.vf4} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-8.c new file mode 100644 index 000000000000..a074caadd02f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vint64m8_t +test (vint8m8_t a, size_t vl) +{ + vint8m1_t b = __riscv_vget_v_i8m8_i8m1 (a, 3); + return __riscv_vsext_vf8_i64m8 (b, vl); +} + +/* { dg-final { scan-assembler-times {vsext\.vf8} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-9.c new file mode 100644 index 000000000000..e5d5401fbda8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-9.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ +/* PR target/127269 */ + +#include "riscv_vector.h" + +/* This test is to ensure there is no ICE during compilation. */ + +vint32m2_t +test (vint16m2_t a, vint32m2_t c, size_t vl) +{ + vint16m1_t b = __riscv_vget_v_i16m2_i16m1 (a, 1); + return __riscv_vwmacc_vv_i32m2 (c, b, b, vl); +} + +/* { dg-final { scan-assembler-times {vwmacc\.vv} 1 } } */
