https://gcc.gnu.org/g:b5ca329230c1db0c80cf13563431e8525dd517a5
commit r17-4216-gb5ca329230c1db0c80cf13563431e8525dd517a5 Author: Claudio Bantaloukas <[email protected]> Date: Mon Sep 14 10:42:58 2026 +0000 aarch64: Rename aarch64_imm3 and aarch64_lane_imm3 predicates Unlike other aarch64_immx predicates that allow using all bits available, aarch64_imm3 was only allowing values up to 4. Since the predicate is only being used in extended register versions of add, adds etc to denote a shift amount, it is best renamed to aarch64_shift_imm3. The aarch64_lane_imm3 is being renamed to aarch64_imm3. gcc/ * config/aarch64/aarch64.md: Rename aarch64_imm3 as aarch64_shift_imm3. * config/aarch64/aarch64-simd.md: Rename aarch64_lane_imm3 as aarch64_imm3. * config/aarch64/predicates.md: Rename aarch64_imm3 as aarch64_shift_imm3 and aarch64_lane_imm3 to aarch64_imm3. Diff: --- gcc/config/aarch64/aarch64-simd.md | 24 ++++++++++++------------ gcc/config/aarch64/aarch64.md | 22 +++++++++++----------- gcc/config/aarch64/predicates.md | 6 +++--- 3 files changed, 26 insertions(+), 26 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 956ca861c944..5e87df2bb5fd 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -10364,7 +10364,7 @@ (unspec:V4SF [(match_operand:V4SF 1 "register_operand") (match_operand:V8HF 2 "register_operand") (match_operand:V8HF 3 "register_operand") - (match_operand:SI 4 "aarch64_lane_imm3")] + (match_operand:SI 4 "aarch64_imm3")] VFMLA16_LOW))] "TARGET_F16FML" { @@ -10384,7 +10384,7 @@ (unspec:V4SF [(match_operand:V4SF 1 "register_operand") (match_operand:V8HF 2 "register_operand") (match_operand:V8HF 3 "register_operand") - (match_operand:SI 4 "aarch64_lane_imm3")] + (match_operand:SI 4 "aarch64_imm3")] VFMLA16_HIGH))] "TARGET_F16FML" { @@ -10410,7 +10410,7 @@ (vec_duplicate:V4HF (vec_select:HF (match_operand:V8HF 3 "register_operand" "x") - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")])))) + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")])))) (match_operand:V4SF 1 "register_operand" "0")))] "TARGET_F16FML" "fmlal\\t%0.4s, %2.4h, %3.h[%5]" @@ -10429,7 +10429,7 @@ (vec_duplicate:V4HF (vec_select:HF (match_operand:V8HF 3 "register_operand" "x") - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")])))) + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")])))) (match_operand:V4SF 1 "register_operand" "0")))] "TARGET_F16FML" "fmlsl\\t%0.4s, %2.4h, %3.h[%5]" @@ -10447,7 +10447,7 @@ (vec_duplicate:V4HF (vec_select:HF (match_operand:V8HF 3 "register_operand" "x") - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")])))) + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")])))) (match_operand:V4SF 1 "register_operand" "0")))] "TARGET_F16FML" "fmlal2\\t%0.4s, %2.4h, %3.h[%5]" @@ -10466,7 +10466,7 @@ (vec_duplicate:V4HF (vec_select:HF (match_operand:V8HF 3 "register_operand" "x") - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")])))) + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")])))) (match_operand:V4SF 1 "register_operand" "0")))] "TARGET_F16FML" "fmlsl2\\t%0.4s, %2.4h, %3.h[%5]" @@ -10478,7 +10478,7 @@ (unspec:V2SF [(match_operand:V2SF 1 "register_operand") (match_operand:V4HF 2 "register_operand") (match_operand:V8HF 3 "register_operand") - (match_operand:SI 4 "aarch64_lane_imm3")] + (match_operand:SI 4 "aarch64_imm3")] VFMLA16_LOW))] "TARGET_F16FML" { @@ -10499,7 +10499,7 @@ (unspec:V2SF [(match_operand:V2SF 1 "register_operand") (match_operand:V4HF 2 "register_operand") (match_operand:V8HF 3 "register_operand") - (match_operand:SI 4 "aarch64_lane_imm3")] + (match_operand:SI 4 "aarch64_imm3")] VFMLA16_HIGH))] "TARGET_F16FML" { @@ -10526,7 +10526,7 @@ (vec_duplicate:V2HF (vec_select:HF (match_operand:V8HF 3 "register_operand" "x") - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")])))) + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")])))) (match_operand:V2SF 1 "register_operand" "0")))] "TARGET_F16FML" "fmlal\\t%0.2s, %2.2h, %3.h[%5]" @@ -10545,7 +10545,7 @@ (vec_duplicate:V2HF (vec_select:HF (match_operand:V8HF 3 "register_operand" "x") - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")])))) + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")])))) (match_operand:V2SF 1 "register_operand" "0")))] "TARGET_F16FML" "fmlsl\\t%0.2s, %2.2h, %3.h[%5]" @@ -10563,7 +10563,7 @@ (vec_duplicate:V2HF (vec_select:HF (match_operand:V8HF 3 "register_operand" "x") - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")])))) + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")])))) (match_operand:V2SF 1 "register_operand" "0")))] "TARGET_F16FML" "fmlal2\\t%0.2s, %2.2h, %3.h[%5]" @@ -10582,7 +10582,7 @@ (vec_duplicate:V2HF (vec_select:HF (match_operand:V8HF 3 "register_operand" "x") - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")])))) + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")])))) (match_operand:V2SF 1 "register_operand" "0")))] "TARGET_F16FML" "fmlsl2\\t%0.2s, %2.2h, %3.h[%5]" diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 4ae5c074cd11..302658c970d2 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3216,7 +3216,7 @@ (plus:GPI (ashift:GPI (ANY_EXTEND:GPI (match_operand:ALLX 1 "register_operand" "r")) - (match_operand 2 "aarch64_imm3" "Ui3")) + (match_operand 2 "aarch64_shift_imm3" "Ui3")) (match_operand:GPI 3 "register_operand" "rk")) (const_int 0))) (set (match_operand:GPI 0 "register_operand" "=rk") @@ -3235,7 +3235,7 @@ (ashift:GPI (ANY_EXTEND:GPI (match_operand:ALLX 2 "register_operand" "r")) - (match_operand 3 "aarch64_imm3" "Ui3"))) + (match_operand 3 "aarch64_shift_imm3" "Ui3"))) (const_int 0))) (set (match_operand:GPI 0 "register_operand" "=rk") (minus:GPI (match_dup 1) @@ -3327,7 +3327,7 @@ [(set (match_operand:GPI 0 "register_operand" "=rk") (plus:GPI (ashift:GPI (ANY_EXTEND:GPI (match_operand:ALLX 1 "register_operand" "r")) - (match_operand 2 "aarch64_imm3" "Ui3")) + (match_operand 2 "aarch64_shift_imm3" "Ui3")) (match_operand:GPI 3 "register_operand" "r")))] "" "add\\t%<GPI:w>0, %<GPI:w>3, %w1, <su>xt<ALLX:extsize> %2" @@ -3340,7 +3340,7 @@ (zero_extend:DI (plus:SI (ashift:SI (ANY_EXTEND:SI (match_operand:SHORT 1 "register_operand" "r")) - (match_operand 2 "aarch64_imm3" "Ui3")) + (match_operand 2 "aarch64_shift_imm3" "Ui3")) (match_operand:SI 3 "register_operand" "r"))))] "" "add\\t%w0, %w3, %w1, <su>xt<SHORT:extsize> %2" @@ -3520,7 +3520,7 @@ [(set (match_operand:GPI 0 "register_operand" "=rk") (plus:GPI (and:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_imm3" "Ui3")) + (match_operand 2 "aarch64_shift_imm3" "Ui3")) (match_operand 3 "const_int_operand" "n")) (match_operand:GPI 4 "register_operand" "r")))] "aarch64_uxt_size (INTVAL (operands[2]), INTVAL (operands[3])) != 0" @@ -3537,7 +3537,7 @@ (zero_extend:DI (plus:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") - (match_operand 2 "aarch64_imm3" "Ui3")) + (match_operand 2 "aarch64_shift_imm3" "Ui3")) (match_operand 3 "const_int_operand" "n")) (match_operand:SI 4 "register_operand" "r"))))] "aarch64_uxt_size (INTVAL (operands[2]), INTVAL (operands[3])) != 0" @@ -3980,7 +3980,7 @@ (minus:GPI (match_operand:GPI 1 "register_operand" "rk") (ashift:GPI (ANY_EXTEND:GPI (match_operand:ALLX 2 "register_operand" "r")) - (match_operand 3 "aarch64_imm3" "Ui3"))))] + (match_operand 3 "aarch64_shift_imm3" "Ui3"))))] "" "sub\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:extsize> %3" [(set_attr "type" "alu_ext")] @@ -3993,7 +3993,7 @@ (minus:SI (match_operand:SI 1 "register_operand" "rk") (ashift:SI (ANY_EXTEND:SI (match_operand:SHORT 2 "register_operand" "r")) - (match_operand 3 "aarch64_imm3" "Ui3")))))] + (match_operand 3 "aarch64_shift_imm3" "Ui3")))))] "" "sub\\t%w0, %w1, %w2, <su>xt<SHORT:extsize> %3" [(set_attr "type" "alu_ext")] @@ -4227,7 +4227,7 @@ (minus:GPI (match_operand:GPI 4 "register_operand" "rk") (and:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_imm3" "Ui3")) + (match_operand 2 "aarch64_shift_imm3" "Ui3")) (match_operand 3 "const_int_operand" "n"))))] "aarch64_uxt_size (INTVAL (operands[2]),INTVAL (operands[3])) != 0" "* @@ -4244,7 +4244,7 @@ (minus:SI (match_operand:SI 4 "register_operand" "rk") (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") - (match_operand 2 "aarch64_imm3" "Ui3")) + (match_operand 2 "aarch64_shift_imm3" "Ui3")) (match_operand 3 "const_int_operand" "n")))))] "aarch64_uxt_size (INTVAL (operands[2]),INTVAL (operands[3])) != 0" "* @@ -4723,7 +4723,7 @@ (compare:CC_SWP (ashift:GPI (ANY_EXTEND:GPI (match_operand:ALLX 0 "register_operand" "r")) - (match_operand 1 "aarch64_imm3" "Ui3")) + (match_operand 1 "aarch64_shift_imm3" "Ui3")) (match_operand:GPI 2 "register_operand" "r")))] "" "cmp\\t%<GPI:w>2, %w0, <su>xt<ALLX:extsize> %1" diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 9d2613a9aeef..6cd809cd615d 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -280,9 +280,9 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "aarch64_shift_imm_di"))) -;; The imm3 field is a 3-bit field that only accepts immediates in the +;; The aarch64_shift_imm3 field is a 3-bit field that only accepts immediates in the ;; range 0..4. -(define_predicate "aarch64_imm3" +(define_predicate "aarch64_shift_imm3" (and (match_code "const_int") (match_test "UINTVAL (op) <= 4"))) @@ -294,7 +294,7 @@ ;; The imm3 field is a 3-bit field that only accepts immediates in the ;; range 0..7. -(define_predicate "aarch64_lane_imm3" +(define_predicate "aarch64_imm3" (and (match_code "const_int") (match_test "UINTVAL (op) <= 7")))
