https://gcc.gnu.org/g:ab5b886f74ea8d5ee223ad5cc3f17e43a16f6099
commit ab5b886f74ea8d5ee223ad5cc3f17e43a16f6099 Author: Michael Meissner <[email protected]> Date: Thu Sep 17 14:05:37 2026 -0400 Remove debug switches. 2026-09-17 Michael Meissner <[email protected]> gcc/ * config/rs6000/float16.md (extendbf<mode>2): Remove BFmode debug switches. (extendbf<mode>2_not_p10): Likewise. (extendbf<mode>2_p10): Likewise. * config/rs6000/rs6000.h (TARGET_BFLOAT16_CVT): Likewise. * config/rs6000/rs6000.opt (-mbfloat16-convert): Likewise. (-mbfloat16-p10-convert): Likewise. Diff: --- gcc/config/rs6000/float16.md | 10 ++++------ gcc/config/rs6000/rs6000.h | 6 ------ gcc/config/rs6000/rs6000.opt | 8 -------- 3 files changed, 4 insertions(+), 20 deletions(-) diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index da1488a807b0..abe88c4ab632 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -250,9 +250,9 @@ [(set (match_operand:SFDF 0 "vsx_register_operand") (float_extend:SFDF (match_operand:BF 1 "gpc_reg_operand")))] - "TARGET_BFLOAT16_CVT" + "TARGET_FLOAT16" { - if (TARGET_BFLOAT16_HW && TARGET_BFLOAT16_P10_CONVERT) + if (TARGET_BFLOAT16_HW) emit_insn (gen_extendbf<mode>2_p10 (operands[0], operands[1])); else emit_insn (gen_extendbf<mode>2_not_p10 (operands[0], operands[1])); @@ -265,8 +265,7 @@ (float_extend:SFDF (match_operand:BF 1 "vsx_register_operand" "wa"))) (clobber (match_scratch:V4SF 2 "=wa"))] - "TARGET_BFLOAT16_HW && TARGET_BFLOAT16_CONVERT - && TARGET_BFLOAT16_P10_CONVERT" + "TARGET_BFLOAT16_HW" "#" "&& 1" [(pc)] @@ -303,8 +302,7 @@ (match_operand:BF 1 "int_reg_operand" "r"))) (clobber (match_scratch:V4SF 2 "=wa")) (clobber (match_scratch:DI 3 "=r"))] - "TARGET_BFLOAT16_CVT - && (!TARGET_BFLOAT16_HW || !TARGET_BFLOAT16_P10_CONVERT)" + "TARGET_FLOAT16 && !TARGET_BFLOAT16_HW" "#" "&& reload_completed" [(pc)] diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index d91b2a564998..1d88e0a46df3 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -355,12 +355,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #define TARGET_BFLOAT16_HW (TARGET_FLOAT16 && TARGET_POWER10) #define TARGET_FLOAT16_HW (TARGET_FLOAT16 && TARGET_P9_VECTOR) -/* Mode iterator for conversions from 16-bit floating point. Unlike - TARGET_BFLOAT16_HW, this specifically allows converting from BFmode even if - we don't have the bfloat16 conversion. We do this conversion */ -#define TARGET_BFLOAT16_CVT \ - (TARGET_FLOAT16 && TARGET_BFLOAT16_CONVERT && TARGET_P9_VECTOR) - /* Do we have conversion support in hardware for the 16-bit floating point and also enable the 16-bit floating point vector optimizations? */ #define TARGET_BFLOAT16_HW_VECTOR \ diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 88d32f72b5a9..40a83a716f08 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -646,14 +646,6 @@ mfloat16 Target Mask(FLOAT16) Var(rs6000_isa_flags) Enable or disable 16-bit floating point. -mbfloat16-convert -Target Undocumented Var(TARGET_BFLOAT16_CONVERT) Init(1) Save -Generate (do not generate) __bf16 to float/double conversions. - -mbfloat16-p10-convert -Target Undocumented Var(TARGET_BFLOAT16_P10_CONVERT) Init(1) Save -Generate (do not generate) xvcvbf16spn to do __bf16 to float/double conversions. - mfloat16-gpr-convert Target Undocumented Mask(FLOAT16_GPR_CONVERT) Var(rs6000_isa_flags) Pass/return (do not pass/return) 16-it float conversions in GPR registers.
