https://gcc.gnu.org/g:11ae0ce305601ebf85b1a09b130cb3e7b46157f9
commit r17-4403-g11ae0ce305601ebf85b1a09b130cb3e7b46157f9 Author: Xi Ruoyao <[email protected]> Date: Thu Sep 3 17:55:51 2026 +0800 LoongArch: fix __builtin_bitreverse16 ICE on LA32R gcc/ * config/loongarch/loongarch.md (bitreverseqi2): Disable on LA32R. gcc/testsuite/ * gcc.target/loongarch/bitreverse-la32r.c: New test. Diff: --- gcc/config/loongarch/loongarch.md | 2 +- gcc/testsuite/gcc.target/loongarch/bitreverse-la32r.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index ecf1563270f5..cccb0ed8612f 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -4771,7 +4771,7 @@ (define_expand "bitreversehi2" [(set (match_operand:HI 0 "register_operand" "=r") (bitreverse:HI (match_operand:HI 1 "register_operand" "r")))] - "" + "TARGET_64BIT || TARGET_32BIT_S" { rtx t = gen_reg_rtx (word_mode); diff --git a/gcc/testsuite/gcc.target/loongarch/bitreverse-la32r.c b/gcc/testsuite/gcc.target/loongarch/bitreverse-la32r.c new file mode 100644 index 000000000000..72180176d685 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/bitreverse-la32r.c @@ -0,0 +1,4 @@ +/* Verify that bitreverse builtins do not ICE on LA32R. */ +/* { dg-do compile } */ +/* { dg-options "-mabi=ilp32s -march=la32rv1.0" } */ +#include "la64/bitreverse.c"
