https://gcc.gnu.org/g:d5a076158aa3da594bc845b8363264d8fcec4a5e
commit r17-4448-gd5a076158aa3da594bc845b8363264d8fcec4a5e Author: Richard Ball <[email protected]> Date: Fri Sep 18 20:06:44 2026 +0100 aarch64: Add support for FEAT_CMH atomic store intrinsics This patch alters the exisiting atomic_store_with_stshh to a generic version atomic_store_with_hint this has allowed for the new hints added by FEAT_CMH to be added to this function as well. gcc/ChangeLog: * config/aarch64/aarch64-builtins.cc (enum aarch64_builtins): Change Function/Builtin names. (aarch64_init_pcdphint_builtins): Likewise. (aarch64_init_atomic_hints_builtins): Likewise. (aarch64_general_init_builtins): Likewise. (aarch64_expand_stshh_builtin): Likewise. (aarch64_expand_atomic_hints_builtins): Likewise. (aarch64_general_expand_builtin): Likewise. (aarch64_resolve_overloaded_builtin_stshh): Likewise. (aarch64_resolve_overloaded_builtin_atomic_hint_store): Likewise (aarch64_resolve_overloaded_builtin_general): Likewise. * config/aarch64/arm_acle.h (__atomic_store_with_stshh): Likewise. (__arm_atomic_store_with_hint): Likewise. * config/aarch64/atomics.md (@aarch64_atomic_store_stshh<mode>): Add new hints to pattern (@aarch64_atomic_hints_store<mode>): Likewise. * config/aarch64/iterators.md: Add Unspec for new hints. gcc/testsuite/ChangeLog: * g++.target/aarch64/atomic_store_with_stshh.C: Change Function name. * gcc.target/aarch64/atomic_store_with_stshh.c: Likewise. * gcc.target/aarch64/atomic_store_with_shuh.c: New test. * gcc.target/aarch64/atomic_store_with_stcph.c: New test. Diff: --- gcc/config/aarch64/aarch64-builtins.cc | 133 ++++++++------- gcc/config/aarch64/arm_acle.h | 6 +- gcc/config/aarch64/atomics.md | 28 +++- gcc/config/aarch64/iterators.md | 2 +- .../g++.target/aarch64/atomic_store_with_stshh.C | 22 +-- .../gcc.target/aarch64/atomic_store_with_shuh.c | 186 +++++++++++++++++++++ .../gcc.target/aarch64/atomic_store_with_stcph.c | 186 +++++++++++++++++++++ .../gcc.target/aarch64/atomic_store_with_stshh.c | 22 +-- 8 files changed, 490 insertions(+), 95 deletions(-) diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index 8a82b131b72c..5b1f9485d352 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -743,14 +743,14 @@ enum aarch64_builtins AARCH64_BUILTIN_GCSPOPM, AARCH64_BUILTIN_GCSSS, /* Armv9.6-A builtins. */ - AARCH64_BUILTIN_STSHH, - AARCH64_BUILTIN_STSHH_QI, - AARCH64_BUILTIN_STSHH_HI, - AARCH64_BUILTIN_STSHH_SI, - AARCH64_BUILTIN_STSHH_DI, - AARCH64_BUILTIN_STSHH_SF, - AARCH64_BUILTIN_STSHH_DF, - AARCH64_BUILTIN_STSHH_PTR, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_QI, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_HI, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SI, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DI, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SF, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DF, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_PTR, /* System Hint Operation builtins. */ AARCH64_BUILTIN_YIELD, AARCH64_BUILTIN_WFE, @@ -2287,10 +2287,10 @@ aarch64_init_gcs_builtins (void) AARCH64_BUILTIN_GCSSS); } -/* Add builtins for FEAT_PCDPHINT. */ +/* Add builtins for atomic hints. */ static void -aarch64_init_pcdphint_builtins (void) +aarch64_init_atomic_hints_builtins (void) { tree ftype; @@ -2298,65 +2298,72 @@ aarch64_init_pcdphint_builtins (void) void_type_node, unsigned_type_node, unsigned_type_node, NULL_TREE); - aarch64_builtin_decls[AARCH64_BUILTIN_STSHH] - = aarch64_general_add_builtin ("__builtin_aarch64_stshh", ftype, - AARCH64_BUILTIN_STSHH); + aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE] + = aarch64_general_add_builtin ("__builtin_aarch64_atomic_hints_store", + ftype, AARCH64_BUILTIN_ATOMIC_HINTS_STORE); ftype = build_function_type_list (void_type_node, ptr_type_node, unsigned_char_type_node, unsigned_type_node, unsigned_type_node, NULL_TREE); - aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_QI] - = aarch64_general_add_builtin ("__builtin_aarch64_stshh_qi", ftype, - AARCH64_BUILTIN_STSHH_QI); + aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_QI] + = aarch64_general_add_builtin ("__builtin_aarch64_atomic_hints_store_qi", + ftype, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_QI); ftype = build_function_type_list (void_type_node, ptr_type_node, short_unsigned_type_node, unsigned_type_node, unsigned_type_node, NULL_TREE); - aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_HI] - = aarch64_general_add_builtin ("__builtin_aarch64_stshh_hi", ftype, - AARCH64_BUILTIN_STSHH_HI); + aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_HI] + = aarch64_general_add_builtin ("__builtin_aarch64_atomic_hints_store_hi", + ftype, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_HI); ftype = build_function_type_list (void_type_node, ptr_type_node, unsigned_type_node, unsigned_type_node, unsigned_type_node, NULL_TREE); - aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_SI] - = aarch64_general_add_builtin ("__builtin_aarch64_stshh_si", ftype, - AARCH64_BUILTIN_STSHH_SI); + aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SI] + = aarch64_general_add_builtin ("__builtin_aarch64_atomic_hints_store_si", + ftype, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SI); ftype = build_function_type_list (void_type_node, ptr_type_node, long_long_unsigned_type_node, unsigned_type_node, unsigned_type_node, NULL_TREE); - aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_DI] - = aarch64_general_add_builtin ("__builtin_aarch64_stshh_di", ftype, - AARCH64_BUILTIN_STSHH_DI); + aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DI] + = aarch64_general_add_builtin ("__builtin_aarch64_atomic_hints_store_di", + ftype, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DI); ftype = build_function_type_list (void_type_node, ptr_type_node, float_type_node, unsigned_type_node, unsigned_type_node, NULL_TREE); - aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_SF] - = aarch64_general_add_builtin ("__builtin_aarch64_stshh_sf", ftype, - AARCH64_BUILTIN_STSHH_SF); + aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SF] + = aarch64_general_add_builtin ("__builtin_aarch64_atomic_hints_store_sf", + ftype, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SF); ftype = build_function_type_list (void_type_node, ptr_type_node, double_type_node, unsigned_type_node, unsigned_type_node, NULL_TREE); - aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_DF] - = aarch64_general_add_builtin ("__builtin_aarch64_stshh_df", ftype, - AARCH64_BUILTIN_STSHH_DF); + aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DF] + = aarch64_general_add_builtin ("__builtin_aarch64_atomic_hints_store_df", + ftype, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DF); ftype = build_function_type_list (void_type_node, ptr_type_node, ptr_type_node, unsigned_type_node, unsigned_type_node, NULL_TREE); - aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_PTR] - = aarch64_general_add_builtin ("__builtin_aarch64_stshh_ptr", ftype, - AARCH64_BUILTIN_STSHH_PTR); + aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_PTR] + = aarch64_general_add_builtin ("__builtin_aarch64_atomic_hints_store_ptr", + ftype, + AARCH64_BUILTIN_ATOMIC_HINTS_STORE_PTR); } @@ -2407,7 +2414,7 @@ aarch64_general_init_builtins (void) AARCH64_BUILTIN_CHKFEAT); aarch64_init_gcs_builtins (); - aarch64_init_pcdphint_builtins (); + aarch64_init_atomic_hints_builtins (); if (in_lto_p) handle_arm_acle_h (); @@ -3940,27 +3947,27 @@ aarch64_expand_tbl_tbx (vec<expand_operand> &ops, unspec unspec) } void -aarch64_expand_stshh_builtin (tree exp, int fcode) +aarch64_expand_atomic_hints_builtins (tree exp, int fcode) { machine_mode mode = TYPE_MODE (TREE_TYPE (CALL_EXPR_ARG (exp, 1))); rtx val = expand_normal (CALL_EXPR_ARG (exp, 1)); rtx mem_order = expand_normal (CALL_EXPR_ARG (exp, 2)); - rtx ret = expand_normal (CALL_EXPR_ARG (exp, 3)); + rtx hint = expand_normal (CALL_EXPR_ARG (exp, 3)); - require_const_argument (exp, 3, 0, 2); + require_const_argument (exp, 3, 0, 5); require_const_argument (exp, 2, 0, 6); if (seen_error ()) return; switch (fcode) { - case AARCH64_BUILTIN_STSHH_SF: + case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SF: { val = force_lowpart_subreg (SImode, val, SFmode); mode = SImode; break; } - case AARCH64_BUILTIN_STSHH_DF: + case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DF: { val = force_lowpart_subreg (DImode, val, DFmode); mode = DImode; @@ -3980,12 +3987,12 @@ aarch64_expand_stshh_builtin (tree exp, int fcode) set_mem_align (mem, GET_MODE_ALIGNMENT (mode)); expand_operand ops[4]; - enum insn_code icode = code_for_aarch64_atomic_store_stshh (mode); + enum insn_code icode; create_output_operand (&ops[0], mem, mode); create_input_operand (&ops[1], val, mode); create_input_operand (&ops[2], mem_order, SImode); - create_input_operand (&ops[3], ret, SImode); - + create_input_operand (&ops[3], hint, SImode); + icode = code_for_aarch64_atomic_hints_store (mode); expand_insn (icode, 4, ops); } @@ -4457,14 +4464,14 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target, case AARCH64_BUILTIN_GCSSS: return aarch64_expand_gcs_builtin (exp, target, fcode, ignore); - case AARCH64_BUILTIN_STSHH_QI: - case AARCH64_BUILTIN_STSHH_HI: - case AARCH64_BUILTIN_STSHH_SI: - case AARCH64_BUILTIN_STSHH_DI: - case AARCH64_BUILTIN_STSHH_SF: - case AARCH64_BUILTIN_STSHH_DF: - case AARCH64_BUILTIN_STSHH_PTR: - aarch64_expand_stshh_builtin (exp, fcode); + case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_QI: + case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_HI: + case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SI: + case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DI: + case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SF: + case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DF: + case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_PTR: + aarch64_expand_atomic_hints_builtins (exp, fcode); return target; } @@ -5442,11 +5449,9 @@ aarch64_resolve_overloaded_memtag (location_t loc, } static tree -aarch64_resolve_overloaded_builtin_stshh (void *pass_params) +aarch64_resolve_overloaded_builtin_atomic_hints (void *pass_params) { vec<tree, va_gc> *params = static_cast<vec<tree, va_gc> *> (pass_params); - if (vec_safe_length (params) != 4) - return NULL_TREE; tree addr = (*params)[0]; tree val = (*params)[1]; @@ -5459,23 +5464,25 @@ aarch64_resolve_overloaded_builtin_stshh (void *pass_params) tree ptr_type = TYPE_MAIN_VARIANT (TREE_TYPE (addr_type)); + if (vec_safe_length (params) != 4) + return NULL_TREE; if (POINTER_TYPE_P (ptr_type)) - return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_PTR]; + return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_PTR]; switch (TYPE_MODE (ptr_type)) { case QImode: - return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_QI]; + return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_QI]; case HImode: - return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_HI]; + return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_HI]; case SImode: - return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_SI]; + return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SI]; case DImode: - return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_DI]; + return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DI]; case SFmode: - return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_SF]; + return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SF]; case DFmode: - return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_DF]; + return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DF]; default: return NULL_TREE; } @@ -5492,8 +5499,8 @@ aarch64_resolve_overloaded_builtin_general (location_t loc, tree function, && fcode <= AARCH64_MEMTAG_BUILTIN_END) return aarch64_resolve_overloaded_memtag(loc, function, pass_params); - if (fcode == AARCH64_BUILTIN_STSHH) - return aarch64_resolve_overloaded_builtin_stshh (pass_params); + if (fcode == AARCH64_BUILTIN_ATOMIC_HINTS_STORE) + return aarch64_resolve_overloaded_builtin_atomic_hints (pass_params); return NULL_TREE; } diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h index b31e23e6cbae..9317f1d2371c 100644 --- a/gcc/config/aarch64/arm_acle.h +++ b/gcc/config/aarch64/arm_acle.h @@ -102,9 +102,9 @@ __sqrtf (float __x) return __builtin_aarch64_sqrtsf (__x); } -#define __atomic_store_with_stshh(__addr, __value, __memory_order, __ret) \ - __builtin_aarch64_stshh ((__addr), (__value), \ - (__memory_order), (__ret)) +#define __arm_atomic_store_with_hint(__addr, __value, __memory_order, __hint) \ + __builtin_aarch64_atomic_hints_store ((__addr), (__value), \ + (__memory_order), (__hint)) #pragma GCC push_options #pragma GCC target ("+nothing+jscvt") diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index 2316fea8135a..dca36242cb01 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -751,19 +751,35 @@ [(set_attr "arch" "*,rcpc8_4")] ) -(define_insn "@aarch64_atomic_store_stshh<mode>" +(define_insn "@aarch64_atomic_hints_store<mode>" [(set (match_operand:ALLI 0 "aarch64_rcpc_memory_operand" "=Q,Ust") (unspec_volatile:ALLI [(match_operand:ALLI 1 "aarch64_reg_or_zero" "rZ,rZ") (match_operand:SI 2 "const_int_operand") ;; model (match_operand:SI 3 "const_int_operand")] ;; ret_policy - UNSPECV_STSHH))] + UNSPECV_ATOMIC_HINTS_STORE))] "" { - if (INTVAL (operands[3]) == 0) - output_asm_insn ("stshh\tkeep", operands); - else - output_asm_insn ("stshh\tstrm", operands); + switch (INTVAL (operands[3])) + { + case 0: + output_asm_insn ("stshh\tkeep", operands); + break; + case 1: + output_asm_insn ("stshh\tstrm", operands); + break; + case 2: + output_asm_insn ("stcph", operands); + break; + case 3: + output_asm_insn ("shuh", operands); + break; + case 4: + output_asm_insn ("shuh\tph", operands); + break; + default: + gcc_unreachable (); + } enum memmodel model = memmodel_from_int (INTVAL (operands[2])); if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model)) return "str<atomic_sfx>\t%<w>1, %0"; diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 8ed91d021f07..eea783ffc081 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1478,7 +1478,7 @@ UNSPECV_LDA ; Represent an atomic load or load-acquire. UNSPECV_LDAP ; Represent an atomic acquire load with RCpc semantics. UNSPECV_STL ; Represent an atomic store or store-release. - UNSPECV_STSHH ; Represent an atomic store with an stshh hint. + UNSPECV_ATOMIC_HINTS_STORE ; Represent an atomic store with a hint. UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap. UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange. UNSPECV_ATOMIC_CAS ; Represent an atomic CAS. diff --git a/gcc/testsuite/g++.target/aarch64/atomic_store_with_stshh.C b/gcc/testsuite/g++.target/aarch64/atomic_store_with_stshh.C index d22412369ef8..5553c5d67df5 100644 --- a/gcc/testsuite/g++.target/aarch64/atomic_store_with_stshh.C +++ b/gcc/testsuite/g++.target/aarch64/atomic_store_with_stshh.C @@ -18,7 +18,7 @@ testFun1 () char* ptr1 = &item1; char test1 = 1; - __atomic_store_with_stshh (ptr1, test1, __ATOMIC_RELAXED, 0); + __arm_atomic_store_with_hint (ptr1, test1, __ATOMIC_RELAXED, 0); } /* @@ -34,7 +34,7 @@ testFun2 () short item2 = 10; short* ptr2 = &item2; short test2 = 11; - __atomic_store_with_stshh (ptr2, test2, __ATOMIC_RELEASE, 0); + __arm_atomic_store_with_hint (ptr2, test2, __ATOMIC_RELEASE, 0); } /* @@ -50,7 +50,7 @@ testFun3 () unsigned int item3 = 10; unsigned int* ptr3 = &item3; unsigned int test3 = 11; - __atomic_store_with_stshh (ptr3, test3, __ATOMIC_SEQ_CST, 1); + __arm_atomic_store_with_hint (ptr3, test3, __ATOMIC_SEQ_CST, 1); } /* @@ -66,7 +66,7 @@ testFun4 () long item4 = 10; long* ptr4 = &item4; long test4 = 11; - __atomic_store_with_stshh (ptr4, test4, __ATOMIC_RELAXED, 1); + __arm_atomic_store_with_hint (ptr4, test4, __ATOMIC_RELAXED, 1); } /* @@ -84,7 +84,7 @@ testFun5 () long **ptr5 = &ptritem; long test5item = 11; long *test5 = &test5item; - __atomic_store_with_stshh (ptr5, test5, __ATOMIC_SEQ_CST, 0); + __arm_atomic_store_with_hint (ptr5, test5, __ATOMIC_SEQ_CST, 0); } /* @@ -100,7 +100,7 @@ testFun6 () float item6 = 10; float* ptr6 = &item6; float test6 = 11; - __atomic_store_with_stshh (ptr6, test6, __ATOMIC_SEQ_CST, 0); + __arm_atomic_store_with_hint (ptr6, test6, __ATOMIC_SEQ_CST, 0); } /* @@ -116,7 +116,7 @@ testFun7 () double item7 = 10; double* ptr7 = &item7; double test7 = 11; - __atomic_store_with_stshh (ptr7, test7, __ATOMIC_RELAXED, 1); + __arm_atomic_store_with_hint (ptr7, test7, __ATOMIC_RELAXED, 1); } /* @@ -133,7 +133,7 @@ testFun8 () char* ptr8 = &item8; long test8 = 1; - __atomic_store_with_stshh (ptr8, test8, __ATOMIC_RELAXED, 0); + __arm_atomic_store_with_hint (ptr8, test8, __ATOMIC_RELAXED, 0); } /* @@ -150,7 +150,7 @@ testFun9 () int* ptr9 = &item9; float test9 = 1; - __atomic_store_with_stshh (ptr9, test9, __ATOMIC_RELAXED, 1); + __arm_atomic_store_with_hint (ptr9, test9, __ATOMIC_RELAXED, 1); } /* @@ -166,7 +166,7 @@ static char buf[8]; void testFun10 (void) { - __atomic_store_with_stshh((buf + 1), (char)7, __ATOMIC_RELAXED, 1); + __arm_atomic_store_with_hint((buf + 1), (char)7, __ATOMIC_RELAXED, 1); } /* @@ -182,5 +182,5 @@ testFun11 () int item11 = 10; int* ptr11 = &item11; - __atomic_store_with_stshh (ptr11, 0, __ATOMIC_RELAXED, 1); + __arm_atomic_store_with_hint (ptr11, 0, __ATOMIC_RELAXED, 1); } diff --git a/gcc/testsuite/gcc.target/aarch64/atomic_store_with_shuh.c b/gcc/testsuite/gcc.target/aarch64/atomic_store_with_shuh.c new file mode 100644 index 000000000000..ce457a85568f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic_store_with_shuh.c @@ -0,0 +1,186 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8-a -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_acle.h> + +/* +** testFun1: +** ... +** shuh +** strb w[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun1 () +{ + char item1 = 0; + char* ptr1 = &item1; + char test1 = 1; + + __arm_atomic_store_with_hint (ptr1, test1, __ATOMIC_RELAXED, 3); +} + +/* +** testFun2: +** ... +** shuh ph +** stlrh w[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun2 () +{ + short item2 = 10; + short* ptr2 = &item2; + short test2 = 11; + __arm_atomic_store_with_hint (ptr2, test2, __ATOMIC_RELEASE, 4); +} + +/* +** testFun3: +** ... +** shuh +** stlr w[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun3 () +{ + unsigned int item3 = 10; + unsigned int* ptr3 = &item3; + unsigned int test3 = 11; + __arm_atomic_store_with_hint (ptr3, test3, __ATOMIC_SEQ_CST, 3); +} + +/* +** testFun4: +** ... +** shuh +** str x[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun4 () +{ + long item4 = 10; + long* ptr4 = &item4; + long test4 = 11; + __arm_atomic_store_with_hint (ptr4, test4, __ATOMIC_RELAXED, 3); +} + +/* +** testFun5: +** ... +** shuh ph +** stlr x[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun5 () +{ + long item5 = 10; + long *ptritem = &item5; + long **ptr5 = &ptritem; + long test5item = 11; + long *test5 = &test5item; + __arm_atomic_store_with_hint (ptr5, test5, __ATOMIC_SEQ_CST, 4); +} + +/* +** testFun6: +** ... +** shuh +** stlr w[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun6 () +{ + float item6 = 10; + float* ptr6 = &item6; + float test6 = 11; + __arm_atomic_store_with_hint (ptr6, test6, __ATOMIC_SEQ_CST, 3); +} + +/* +** testFun7: +** ... +** shuh ph +** str x[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun7 () +{ + double item7 = 10; + double* ptr7 = &item7; + double test7 = 11; + __arm_atomic_store_with_hint (ptr7, test7, __ATOMIC_RELAXED, 4); +} + +/* +** testFun8: +** ... +** shuh ph +** strb w[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun8 () +{ + char item8 = 0; + char* ptr8 = &item8; + long test8 = 1; + + __arm_atomic_store_with_hint (ptr8, test8, __ATOMIC_RELAXED, 4); +} + +/* +** testFun9: +** ... +** shuh +** str w[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun9 () +{ + int item9 = 0; + int* ptr9 = &item9; + float test9 = 1; + + __arm_atomic_store_with_hint (ptr9, test9, __ATOMIC_RELAXED, 3); +} + +/* +** testFun10: +** ... +** add (x[0-9]+), \1, 1 +** mov (w[0-9]+), 7 +** shuh +** strb \2, \[\1\] +** ... +*/ +static char buf[8]; +void +testFun10 (void) +{ + __arm_atomic_store_with_hint((buf + 1), (char)7, __ATOMIC_RELAXED, 3); +} + +/* +** testFun11: +** ... +** shuh +** str wzr, \[x[0-9]+\] +** ... +*/ +void +testFun11 () +{ + int item11 = 10; + int* ptr11 = &item11; + + __arm_atomic_store_with_hint (ptr11, 0, __ATOMIC_RELAXED, 3); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stcph.c b/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stcph.c new file mode 100644 index 000000000000..a762da3e1f61 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stcph.c @@ -0,0 +1,186 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8-a -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_acle.h> + +/* +** testFun1: +** ... +** stcph +** strb w[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun1 () +{ + char item1 = 0; + char* ptr1 = &item1; + char test1 = 1; + + __arm_atomic_store_with_hint (ptr1, test1, __ATOMIC_RELAXED, 2); +} + +/* +** testFun2: +** ... +** stcph +** stlrh w[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun2 () +{ + short item2 = 10; + short* ptr2 = &item2; + short test2 = 11; + __arm_atomic_store_with_hint (ptr2, test2, __ATOMIC_RELEASE, 2); +} + +/* +** testFun3: +** ... +** stcph +** stlr w[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun3 () +{ + unsigned int item3 = 10; + unsigned int* ptr3 = &item3; + unsigned int test3 = 11; + __arm_atomic_store_with_hint (ptr3, test3, __ATOMIC_SEQ_CST, 2); +} + +/* +** testFun4: +** ... +** stcph +** str x[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun4 () +{ + long item4 = 10; + long* ptr4 = &item4; + long test4 = 11; + __arm_atomic_store_with_hint (ptr4, test4, __ATOMIC_RELAXED, 2); +} + +/* +** testFun5: +** ... +** stcph +** stlr x[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun5 () +{ + long item5 = 10; + long *ptritem = &item5; + long **ptr5 = &ptritem; + long test5item = 11; + long *test5 = &test5item; + __arm_atomic_store_with_hint (ptr5, test5, __ATOMIC_SEQ_CST, 2); +} + +/* +** testFun6: +** ... +** stcph +** stlr w[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun6 () +{ + float item6 = 10; + float* ptr6 = &item6; + float test6 = 11; + __arm_atomic_store_with_hint (ptr6, test6, __ATOMIC_SEQ_CST, 2); +} + +/* +** testFun7: +** ... +** stcph +** str x[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun7 () +{ + double item7 = 10; + double* ptr7 = &item7; + double test7 = 11; + __arm_atomic_store_with_hint (ptr7, test7, __ATOMIC_RELAXED, 2); +} + +/* +** testFun8: +** ... +** stcph +** strb w[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun8 () +{ + char item8 = 0; + char* ptr8 = &item8; + long test8 = 1; + + __arm_atomic_store_with_hint (ptr8, test8, __ATOMIC_RELAXED, 2); +} + +/* +** testFun9: +** ... +** stcph +** str w[0-9]+, \[x[0-9]+\] +** ... +*/ +void +testFun9 () +{ + int item9 = 0; + int* ptr9 = &item9; + float test9 = 1; + + __arm_atomic_store_with_hint (ptr9, test9, __ATOMIC_RELAXED, 2); +} + +/* +** testFun10: +** ... +** add (x[0-9]+), \1, 1 +** mov (w[0-9]+), 7 +** stcph +** strb \2, \[\1\] +** ... +*/ +static char buf[8]; +void +testFun10 (void) +{ + __arm_atomic_store_with_hint((buf + 1), (char)7, __ATOMIC_RELAXED, 2); +} + +/* +** testFun11: +** ... +** stcph +** str wzr, \[x[0-9]+\] +** ... +*/ +void +testFun11 () +{ + int item11 = 10; + int* ptr11 = &item11; + + __arm_atomic_store_with_hint (ptr11, 0, __ATOMIC_RELAXED, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stshh.c b/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stshh.c index 516a45aa7811..3948ffcef280 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stshh.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stshh.c @@ -18,7 +18,7 @@ testFun1 () char* ptr1 = &item1; char test1 = 1; - __atomic_store_with_stshh (ptr1, test1, __ATOMIC_RELAXED, 0); + __arm_atomic_store_with_hint (ptr1, test1, __ATOMIC_RELAXED, 0); } /* @@ -34,7 +34,7 @@ testFun2 () short item2 = 10; short* ptr2 = &item2; short test2 = 11; - __atomic_store_with_stshh (ptr2, test2, __ATOMIC_RELEASE, 0); + __arm_atomic_store_with_hint (ptr2, test2, __ATOMIC_RELEASE, 0); } /* @@ -50,7 +50,7 @@ testFun3 () unsigned int item3 = 10; unsigned int* ptr3 = &item3; unsigned int test3 = 11; - __atomic_store_with_stshh (ptr3, test3, __ATOMIC_SEQ_CST, 1); + __arm_atomic_store_with_hint (ptr3, test3, __ATOMIC_SEQ_CST, 1); } /* @@ -66,7 +66,7 @@ testFun4 () long item4 = 10; long* ptr4 = &item4; long test4 = 11; - __atomic_store_with_stshh (ptr4, test4, __ATOMIC_RELAXED, 1); + __arm_atomic_store_with_hint (ptr4, test4, __ATOMIC_RELAXED, 1); } /* @@ -84,7 +84,7 @@ testFun5 () long **ptr5 = &ptritem; long test5item = 11; long *test5 = &test5item; - __atomic_store_with_stshh (ptr5, test5, __ATOMIC_SEQ_CST, 0); + __arm_atomic_store_with_hint (ptr5, test5, __ATOMIC_SEQ_CST, 0); } /* @@ -100,7 +100,7 @@ testFun6 () float item6 = 10; float* ptr6 = &item6; float test6 = 11; - __atomic_store_with_stshh (ptr6, test6, __ATOMIC_SEQ_CST, 0); + __arm_atomic_store_with_hint (ptr6, test6, __ATOMIC_SEQ_CST, 0); } /* @@ -116,7 +116,7 @@ testFun7 () double item7 = 10; double* ptr7 = &item7; double test7 = 11; - __atomic_store_with_stshh (ptr7, test7, __ATOMIC_RELAXED, 1); + __arm_atomic_store_with_hint (ptr7, test7, __ATOMIC_RELAXED, 1); } /* @@ -133,7 +133,7 @@ testFun8 () char* ptr8 = &item8; long test8 = 1; - __atomic_store_with_stshh (ptr8, test8, __ATOMIC_RELAXED, 0); + __arm_atomic_store_with_hint (ptr8, test8, __ATOMIC_RELAXED, 0); } /* @@ -150,7 +150,7 @@ testFun9 () int* ptr9 = &item9; float test9 = 1; - __atomic_store_with_stshh (ptr9, test9, __ATOMIC_RELAXED, 1); + __arm_atomic_store_with_hint (ptr9, test9, __ATOMIC_RELAXED, 1); } /* @@ -166,7 +166,7 @@ static char buf[8]; void testFun10 (void) { - __atomic_store_with_stshh((buf + 1), (char)7, __ATOMIC_RELAXED, 1); + __arm_atomic_store_with_hint((buf + 1), (char)7, __ATOMIC_RELAXED, 1); } /* @@ -182,5 +182,5 @@ testFun11 () int item11 = 10; int* ptr11 = &item11; - __atomic_store_with_stshh (ptr11, 0, __ATOMIC_RELAXED, 1); + __arm_atomic_store_with_hint (ptr11, 0, __ATOMIC_RELAXED, 1); }
