https://gcc.gnu.org/g:611705766efc7ea1dc2fa01e344db20e06546a27
commit r17-4547-g611705766efc7ea1dc2fa01e344db20e06546a27 Author: Pan Li <[email protected]> Date: Mon Sep 21 10:34:22 2026 +0800 RISC-V: Fix ICE for widening insn when dest nregs is less than src [PR target/127269] The function riscv_v_widen_constraint_ok asserts the nregs of the dest must be greater than that of the src when they are different. That is not always true, for example the vwmacc.vx with the src comes from the vget of one wider vector register group. Then we may have the dest takes 2 registers while the src takes 4 registers, and result in the ICE as below. during RTL pass: reload pr127269-18.c:14:1: internal compiler error: in riscv_v_widen_constraint_ok, at config/riscv/riscv-v.cc:6575 Thus, take the register overlap as not allowed instead of the assertion when the nregs of the dest is less than that of the src. PR target/127269 gcc/ChangeLog: * config/riscv/riscv-v.cc (riscv_v_widen_constraint_ok): Return false instead of assertion when the nregs of the dest is less than that of the src. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/config/riscv/riscv-v.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index faa43f4bf649..dd453aa320b6 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -6570,8 +6570,9 @@ riscv_v_widen_constraint_ok (unsigned int regno, machine_mode mode, if (wide_nregs == nregs) return nregs == 1; /* Only allow dest LMUL <= 1. */ + else if (wide_nregs < nregs) + return false; - gcc_checking_assert (wide_nregs > nregs); gcc_checking_assert ((wide_nregs % nregs) == 0); /* No overlap. */
