https://gcc.gnu.org/g:6e82949c656b32424e50123a48bdcd018200b401
commit r17-4620-g6e82949c656b32424e50123a48bdcd018200b401 Author: Pan Li <[email protected]> Date: Tue Sep 22 20:11:19 2026 +0800 RISC-V: Add test cases for vfwmul.vv reg overlap Add test cases for register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-mf2.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../rvv/autovec/group_overlap/vfwmul_vv-f16-m1.c | 17 +++++++++++++++++ .../rvv/autovec/group_overlap/vfwmul_vv-f16-m2.c | 17 +++++++++++++++++ .../rvv/autovec/group_overlap/vfwmul_vv-f16-m4.c | 17 +++++++++++++++++ .../rvv/autovec/group_overlap/vfwmul_vv-f16-mf2.c | 19 +++++++++++++++++++ .../rvv/autovec/group_overlap/vfwmul_vv-f16-mf4.c | 19 +++++++++++++++++++ .../rvv/autovec/group_overlap/vfwmul_vv-f32-m1.c | 17 +++++++++++++++++ .../rvv/autovec/group_overlap/vfwmul_vv-f32-m2.c | 17 +++++++++++++++++ .../rvv/autovec/group_overlap/vfwmul_vv-f32-m4.c | 17 +++++++++++++++++ .../rvv/autovec/group_overlap/vfwmul_vv-f32-mf2.c | 19 +++++++++++++++++++ 9 files changed, 159 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-m1.c new file mode 100644 index 000000000000..483d1c2f848f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e16m1, + vfloat16m1_t, + vfloat32m2_t, + __riscv_vle16_v_f16m1, + __riscv_vfwmul_vv_f32m2, + __riscv_vse32_v_f32m2, + vfwmul_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-m2.c new file mode 100644 index 000000000000..0577ca21b782 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e16m2, + vfloat16m2_t, + vfloat32m4_t, + __riscv_vle16_v_f16m2, + __riscv_vfwmul_vv_f32m4, + __riscv_vse32_v_f32m4, + vfwmul_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-m4.c new file mode 100644 index 000000000000..000ca99d4c57 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-m4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e16m4, + vfloat16m4_t, + vfloat32m8_t, + __riscv_vle16_v_f16m4, + __riscv_vfwmul_vv_f32m8, + __riscv_vse32_v_f32m8, + vfwmul_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-mf2.c new file mode 100644 index 000000000000..e2bea29f8403 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-mf2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e16m1, + vfloat16mf2_t, + vfloat32m1_t, + __riscv_vle16_v_f16mf2, + __riscv_vfwmul_vv_f32m1, + __riscv_vse32_v_f32m1, + vfwmul_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vfwmul\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vfwmul\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-mf4.c new file mode 100644 index 000000000000..9be56d76b829 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f16-mf4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e16m1, + vfloat16mf4_t, + vfloat32mf2_t, + __riscv_vle16_v_f16mf4, + __riscv_vfwmul_vv_f32mf2, + __riscv_vse32_v_f32mf2, + vfwmul_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vfwmul\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vfwmul\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-m1.c new file mode 100644 index 000000000000..20a3d839d9f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e32m1, + vfloat32m1_t, + vfloat64m2_t, + __riscv_vle32_v_f32m1, + __riscv_vfwmul_vv_f64m2, + __riscv_vse64_v_f64m2, + vfwmul_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-m2.c new file mode 100644 index 000000000000..0183ae2be203 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e32m2, + vfloat32m2_t, + vfloat64m4_t, + __riscv_vle32_v_f32m2, + __riscv_vfwmul_vv_f64m4, + __riscv_vse64_v_f64m4, + vfwmul_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-m4.c new file mode 100644 index 000000000000..db73ccfc3463 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-m4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e32m4, + vfloat32m4_t, + vfloat64m8_t, + __riscv_vle32_v_f32m4, + __riscv_vfwmul_vv_f64m8, + __riscv_vse64_v_f64m8, + vfwmul_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-mf2.c new file mode 100644 index 000000000000..33a73f0310b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmul_vv-f32-mf2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e32m1, + vfloat32mf2_t, + vfloat64m1_t, + __riscv_vle32_v_f32mf2, + __riscv_vfwmul_vv_f64m1, + __riscv_vse64_v_f64m1, + vfwmul_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vfwmul\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vfwmul\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
