https://gcc.gnu.org/g:aa141f17fbab704e17e6c6cc046db91155b7bd21
commit r17-4637-gaa141f17fbab704e17e6c6cc046db91155b7bd21 Author: Andrea Pinski <[email protected]> Date: Thu Sep 24 21:15:41 2026 +0000 aarch64: Fix aarch64_evpc_rev64_ext for testing_p case [PR127599] r17-3712-g4182cf11e1e3d2 added some code to expand a perm based on if we are in a loop or not. The problem is in the testing case, the expanding stmt might not have a bb associated with it and that causes an ICE. This fixes the issue by moving the check for testing before the test of inside the loop. Pushed as obvious after bootstrapped and testing on aarch64-linux-gnu. PR target/127599 gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_evpc_rev64_ext): Move the testing_p after the is_bb_in_loop test. gcc/testsuite/ChangeLog: * gcc.dg/torture/pr127599-1.c: New testcase. * gcc.target/aarch64/advsimd-intrinsics/pr127599-1.c: New testcase. Signed-off-by: Andrea Pinski <[email protected]> Diff: --- gcc/config/aarch64/aarch64.cc | 6 +++--- gcc/testsuite/gcc.dg/torture/pr127599-1.c | 9 +++++++++ .../gcc.target/aarch64/advsimd-intrinsics/pr127599-1.c | 11 +++++++++++ 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 2ca834c92b16..705c5378bac6 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -28509,12 +28509,12 @@ aarch64_evpc_rev64_ext (struct expand_vec_perm_d *d) if (!d->perm.series_p (0, 1, nelt - 1, -1)) return false; - if (is_bb_in_loop (gimple_bb (currently_expanding_gimple_stmt))) - return false; - if (d->testing_p) return true; + if (is_bb_in_loop (gimple_bb (currently_expanding_gimple_stmt))) + return false; + rtx tmp1 = gen_reg_rtx (d->vmode); rtx tmp2 = gen_reg_rtx (V16QImode); rtx unspec_rev64 diff --git a/gcc/testsuite/gcc.dg/torture/pr127599-1.c b/gcc/testsuite/gcc.dg/torture/pr127599-1.c new file mode 100644 index 000000000000..e7ad356c356c --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr127599-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* PR target/127599 */ + +#define vector(s,t) t __attribute__((vector_size(s*sizeof(t)))) +vector(4,int) b1; +void c1() { + b1 = __builtin_shufflevector (b1, b1, 1,0,3,2); + b1 = __builtin_shufflevector (b1, b1, 2,3,4,5); +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/pr127599-1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/pr127599-1.c new file mode 100644 index 000000000000..fdeb0f7352c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/pr127599-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O1" } */ +/* PR target/127599 */ + +#include <arm_neon.h> + +int32x4_t b; +void c() { + b = vrev64q_s32(b); + b = vextq_s32(b, b, 2); +}
