https://gcc.gnu.org/g:0de4790181fcf74665c3c27e901559a16d3e4991
commit r17-4670-g0de4790181fcf74665c3c27e901559a16d3e4991 Author: Michiel Derhaeg <[email protected]> Date: Mon Sep 21 16:17:00 2026 +0200 RISC-V: Update ARC-V RMX-100 load latency The old latency is more of a worst-case. Better to optimize for the likely case. Also update branding as the ARC brand+ip has been acquired by MIPS. gcc/ChangeLog: * config/riscv/arcv-rmx100.md (arcv_rmx100_load_insn): Update latency. (arcv_rmx100_fpload_insn): Merge with *_load_insn. Signed-off-by: Michiel Derhaeg <[email protected]> Diff: --- gcc/config/riscv/arcv-rmx100.md | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/gcc/config/riscv/arcv-rmx100.md b/gcc/config/riscv/arcv-rmx100.md index e573a456db1e..fb34d1202e46 100644 --- a/gcc/config/riscv/arcv-rmx100.md +++ b/gcc/config/riscv/arcv-rmx100.md @@ -1,4 +1,4 @@ -;; DFA scheduling description of the Synopsys RMX-100 cpu +;; DFA scheduling description of the ARC-V RMX-100 cpu ;; for GNU C compiler ;; Copyright (C) 2026 Free Software Foundation, Inc. @@ -51,9 +51,9 @@ (eq_attr "type" "imul")) "arcv_rmx100_MPY") -(define_insn_reservation "arcv_rmx100_load_insn" 3 +(define_insn_reservation "arcv_rmx100_load_insn" 1 (and (eq_attr "tune" "arcv_rmx100") - (eq_attr "type" "load")) + (eq_attr "type" "load,fpload")) "arcv_rmx100_DMP") (define_insn_reservation "arcv_rmx100_store_insn" 1 @@ -63,11 +63,6 @@ ;; FPU scheduling. This is based on the "fast" unit for now. -(define_insn_reservation "arcv_rmx100_fpload_insn" 3 - (and (eq_attr "tune" "arcv_rmx100") - (eq_attr "type" "fpload")) - "arcv_rmx100_DMP") - (define_insn_reservation "arcv_rmx100_farith_insn" 2 (and (eq_attr "tune" "arcv_rmx100") (eq_attr "type" "fadd,fcmp"))
