https://gcc.gnu.org/g:a3f5541bcf62d1142cea7f7f70afcabf888d947c
commit r17-4729-ga3f5541bcf62d1142cea7f7f70afcabf888d947c Author: Pan Li <[email protected]> Date: Mon Sep 28 10:30:37 2026 +0800 RISC-V: Allow RVV register overlap for vfw{add,sub,mul}.vf Like vfw{add,sub,mul}.vv, allow the rvv register overlap for the dual widen float vf insns, aka vfwadd.vf, vfwsub.vf and vfwmul.vf. gcc/ChangeLog: * config/riscv/vector.md: Leverage Wvr constraint. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/config/riscv/vector.md | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 37f7b94604d3..a3eeb84231ba 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7318,25 +7318,25 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_dual_widen_<optab><mode>_scalar" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr, vd, vd") (if_then_else:VWEXTF (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rvl, rvl") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (match_operand 9 "const_int_operand" " i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "Wc1,Wc1, vm, vm") + (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_widen_binop:VWEXTF (float_extend:VWEXTF - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr")) + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "Wvr,Wvr,Wvr,Wvr")) (vec_duplicate:VWEXTF (float_extend:<VEL> - (match_operand:<VSUBEL> 4 "register_operand" " f, f")))) - (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] + (match_operand:<VSUBEL> 4 "register_operand" " f, f, f, f")))) + (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfw<insn>.vf\t%0,%3,%4%p1" [(set_attr "type" "vf<widen_binop_insn_type>")
