https://gcc.gnu.org/g:3d5f011ffec35d928577f5cfd24c101c5950ae93
commit r17-4730-g3d5f011ffec35d928577f5cfd24c101c5950ae93 Author: Pan Li <[email protected]> Date: Mon Sep 28 10:30:46 2026 +0800 RISC-V: Add test cases for vfwadd.vf reg overlap Add test cases for register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-mf2.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../rvv/autovec/group_overlap/vfwadd_vf-f16-m1.c | 18 ++++++++++++++++++ .../rvv/autovec/group_overlap/vfwadd_vf-f16-m2.c | 18 ++++++++++++++++++ .../rvv/autovec/group_overlap/vfwadd_vf-f16-m4.c | 18 ++++++++++++++++++ .../rvv/autovec/group_overlap/vfwadd_vf-f16-mf2.c | 19 +++++++++++++++++++ .../rvv/autovec/group_overlap/vfwadd_vf-f16-mf4.c | 19 +++++++++++++++++++ .../rvv/autovec/group_overlap/vfwadd_vf-f32-m1.c | 18 ++++++++++++++++++ .../rvv/autovec/group_overlap/vfwadd_vf-f32-m2.c | 18 ++++++++++++++++++ .../rvv/autovec/group_overlap/vfwadd_vf-f32-m4.c | 18 ++++++++++++++++++ .../rvv/autovec/group_overlap/vfwadd_vf-f32-mf2.c | 19 +++++++++++++++++++ 9 files changed, 165 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-m1.c new file mode 100644 index 000000000000..a2d6577fa9a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-m1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_3( + __riscv_vsetvlmax_e16m1, + vfloat16m1_t, + vfloat32m2_t, + _Float16, + __riscv_vle16_v_f16m1, + __riscv_vfwadd_vf_f32m2, + __riscv_vse32_v_f32m2, + vfwadd_vf, + LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16) + +/* { dg-final { scan-assembler-times {vfwadd\.vf\s+v0,v1,} 1 } } */ +/* { dg-final { scan-assembler-times {vfwadd\.vf\s+v2,v3,} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-m2.c new file mode 100644 index 000000000000..6047d6d1c670 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-m2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_3( + __riscv_vsetvlmax_e16m2, + vfloat16m2_t, + vfloat32m4_t, + _Float16, + __riscv_vle16_v_f16m2, + __riscv_vfwadd_vf_f32m4, + __riscv_vse32_v_f32m4, + vfwadd_vf, + LOOP_DUAL_WIDEN_BINARY_VX_BODY_X8) + +/* { dg-final { scan-assembler-times {vfwadd\.vf\s+v0,v2,} 1 } } */ +/* { dg-final { scan-assembler-times {vfwadd\.vf\s+v4,v6,} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-m4.c new file mode 100644 index 000000000000..ad19ae7c9211 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-m4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_3( + __riscv_vsetvlmax_e16m4, + vfloat16m4_t, + vfloat32m8_t, + _Float16, + __riscv_vle16_v_f16m4, + __riscv_vfwadd_vf_f32m8, + __riscv_vse32_v_f32m8, + vfwadd_vf, + LOOP_DUAL_WIDEN_BINARY_VX_BODY_X4) + +/* { dg-final { scan-assembler-times {vfwadd\.vf\s+v0,v4,} 1 } } */ +/* { dg-final { scan-assembler-times {vfwadd\.vf\s+v8,v12,} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-mf2.c new file mode 100644 index 000000000000..d5a9b74d27ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-mf2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_3( + __riscv_vsetvlmax_e16m1, + vfloat16mf2_t, + vfloat32m1_t, + _Float16, + __riscv_vle16_v_f16mf2, + __riscv_vfwadd_vf_f32m1, + __riscv_vse32_v_f32m1, + vfwadd_vf, + LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap the source at all. */ +/* { dg-final { scan-assembler-not {vfwadd\.vf\s+(v[0-9]+),\1,} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-mf4.c new file mode 100644 index 000000000000..49d6baade47d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f16-mf4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_3( + __riscv_vsetvlmax_e16m1, + vfloat16mf4_t, + vfloat32mf2_t, + _Float16, + __riscv_vle16_v_f16mf4, + __riscv_vfwadd_vf_f32mf2, + __riscv_vse32_v_f32mf2, + vfwadd_vf, + LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap the source at all. */ +/* { dg-final { scan-assembler-not {vfwadd\.vf\s+(v[0-9]+),\1,} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-m1.c new file mode 100644 index 000000000000..a1ed46cba12a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-m1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_3( + __riscv_vsetvlmax_e32m1, + vfloat32m1_t, + vfloat64m2_t, + float, + __riscv_vle32_v_f32m1, + __riscv_vfwadd_vf_f64m2, + __riscv_vse64_v_f64m2, + vfwadd_vf, + LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16) + +/* { dg-final { scan-assembler-times {vfwadd\.vf\s+v0,v1,} 1 } } */ +/* { dg-final { scan-assembler-times {vfwadd\.vf\s+v2,v3,} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-m2.c new file mode 100644 index 000000000000..8d64e80f520f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-m2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_3( + __riscv_vsetvlmax_e32m2, + vfloat32m2_t, + vfloat64m4_t, + float, + __riscv_vle32_v_f32m2, + __riscv_vfwadd_vf_f64m4, + __riscv_vse64_v_f64m4, + vfwadd_vf, + LOOP_DUAL_WIDEN_BINARY_VX_BODY_X8) + +/* { dg-final { scan-assembler-times {vfwadd\.vf\s+v0,v2,} 1 } } */ +/* { dg-final { scan-assembler-times {vfwadd\.vf\s+v4,v6,} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-m4.c new file mode 100644 index 000000000000..3ec51979e0a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-m4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_3( + __riscv_vsetvlmax_e32m4, + vfloat32m4_t, + vfloat64m8_t, + float, + __riscv_vle32_v_f32m4, + __riscv_vfwadd_vf_f64m8, + __riscv_vse64_v_f64m8, + vfwadd_vf, + LOOP_DUAL_WIDEN_BINARY_VX_BODY_X4) + +/* { dg-final { scan-assembler-times {vfwadd\.vf\s+v0,v4,} 1 } } */ +/* { dg-final { scan-assembler-times {vfwadd\.vf\s+v8,v12,} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-mf2.c new file mode 100644 index 000000000000..e41e663b0a9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwadd_vf-f32-mf2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_3( + __riscv_vsetvlmax_e32m1, + vfloat32mf2_t, + vfloat64m1_t, + float, + __riscv_vle32_v_f32mf2, + __riscv_vfwadd_vf_f64m1, + __riscv_vse64_v_f64m1, + vfwadd_vf, + LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap the source at all. */ +/* { dg-final { scan-assembler-not {vfwadd\.vf\s+(v[0-9]+),\1,} } } */
