https://gcc.gnu.org/g:6cf4202e212a0d83ee8bb75e1d03ecc81c25a8b6
commit r17-4799-g6cf4202e212a0d83ee8bb75e1d03ecc81c25a8b6 Author: Karl Meakin <[email protected]> Date: Thu Sep 24 17:54:09 2026 +0000 aarch64: Port NEON SM3 and SM4 intrinsics to pragma-based framework Port the SM3 and SM4 intrinsics (FEAT_SM4) to the pragma-based framework and add assembly tests for each intrinsic. gcc/ChangeLog: * config/aarch64/aarch64-neon-builtins-base.def (vsm3ss1q, vsm3tt1aq, vsm3tt1bq, vsm3tt2aq, vsm3tt2bq, vsm3partw1q, vsm3partw2q, vsm4eq, vsm4ekeyq): New function declarations. * config/aarch64/aarch64-neon-builtins-base.cc (vsm3ss1q, vsm3tt1aq, vsm3tt1bq, vsm3tt2aq, vsm3tt2bq, vsm3partw1q, vsm3partw2q, vsm4eq, vsm4ekeyq): New function bases: * config/aarch64/aarch64-simd-builtins.def (sm3ss1q, sm3tt1aq, sm3tt1bq, sm3tt2aq, sm3tt2bq, sm3partw1q, sm3partw2q, sm4eq, sm4ekeyq): Delete builtin functions. * config/aarch64/arm_neon.h (vsm3ss1q_u32, vsm3tt1aq_u32, vsm3tt1bq_u32, vsm3tt2aq_u32, vsm3tt2bq_u32, vsm3partw1q_u32, vsm3partw2q_u32, vsm4eq_u32, vsm4ekeyq_u32): Delete function definitions. * config/aarch64/aarch64-builtins.cc (aarch64_types_quadopu_imm_qualifiers, TYPES_QUADOPUI): Delete now unused array and macro. gcc/testsuite/ChangeLog: * gcc.target/aarch64/neon/arm_neon_test.h: Set `+sm4` target flag. * gcc.target/aarch64/neon/vsm3.c: New test. * gcc.target/aarch64/neon/vsm4.c: New test. Diff: --- gcc/config/aarch64/aarch64-builtins.cc | 6 -- gcc/config/aarch64/aarch64-neon-builtins-base.cc | 13 ++++ gcc/config/aarch64/aarch64-neon-builtins-base.def | 17 +++++ gcc/config/aarch64/aarch64-simd-builtins.def | 15 ---- gcc/config/aarch64/arm_neon.h | 67 ------------------ .../gcc.target/aarch64/neon/arm_neon_test.h | 2 +- gcc/testsuite/gcc.target/aarch64/neon/vsm3.c | 81 ++++++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/neon/vsm4.c | 26 +++++++ 8 files changed, 138 insertions(+), 89 deletions(-) diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index 9e4b4a9d58fb..148cf0ecd1be 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -336,12 +336,6 @@ aarch64_types_quadopsssu_lane_quadtup_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define TYPES_QUADOPSSSU_LANE_QUADTUP \ (aarch64_types_quadopsssu_lane_quadtup_qualifiers) -static enum aarch64_type_qualifiers -aarch64_types_quadopu_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, - qualifier_unsigned, qualifier_immediate }; -#define TYPES_QUADOPUI (aarch64_types_quadopu_imm_qualifiers) - static enum aarch64_type_qualifiers aarch64_types_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_immediate }; diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.cc b/gcc/config/aarch64/aarch64-neon-builtins-base.cc index b6ec01704e1e..05039cd73845 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.cc @@ -817,4 +817,17 @@ NEON_FUNCTION (vsha512hq, gimple_exact_insn<CODE_FOR_aarch64_crypto_sha512hqv2 NEON_FUNCTION (vsha512h2q, gimple_exact_insn<CODE_FOR_aarch64_crypto_sha512h2qv2di>,) NEON_FUNCTION (vsha512su0q, gimple_exact_insn<CODE_FOR_aarch64_crypto_sha512su0qv2di>,) NEON_FUNCTION (vsha512su1q, gimple_exact_insn<CODE_FOR_aarch64_crypto_sha512su1qv2di>,) + +// SM3 +NEON_FUNCTION (vsm3ss1q, gimple_exact_insn<CODE_FOR_aarch64_sm3ss1qv4si>,) +NEON_FUNCTION (vsm3tt1aq, gimple_exact_insn<CODE_FOR_aarch64_sm3tt1aqv4si>,) +NEON_FUNCTION (vsm3tt1bq, gimple_exact_insn<CODE_FOR_aarch64_sm3tt1bqv4si>,) +NEON_FUNCTION (vsm3tt2aq, gimple_exact_insn<CODE_FOR_aarch64_sm3tt2aqv4si>,) +NEON_FUNCTION (vsm3tt2bq, gimple_exact_insn<CODE_FOR_aarch64_sm3tt2bqv4si>,) +NEON_FUNCTION (vsm3partw1q, gimple_exact_insn<CODE_FOR_aarch64_sm3partw1qv4si>,) +NEON_FUNCTION (vsm3partw2q, gimple_exact_insn<CODE_FOR_aarch64_sm3partw2qv4si>,) + +// SM4 +NEON_FUNCTION (vsm4eq, gimple_exact_insn<CODE_FOR_aarch64_sm4eqv4si>,) +NEON_FUNCTION (vsm4ekeyq, gimple_exact_insn<CODE_FOR_aarch64_sm4ekeyqv4si>,) } diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.def b/gcc/config/aarch64/aarch64-neon-builtins-base.def index 48f4c73897e7..57ef9ce7e492 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.def +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.def @@ -178,4 +178,21 @@ DEF_NEON_FUNCTION (vsha512hq, d_unsigned, ("Q0,Q0,Q0,Q0")) DEF_NEON_FUNCTION (vsha512h2q, d_unsigned, ("Q0,Q0,Q0,Q0")) DEF_NEON_FUNCTION (vsha512su0q, d_unsigned, ("Q0,Q0,Q0")) DEF_NEON_FUNCTION (vsha512su1q, d_unsigned, ("Q0,Q0,Q0,Q0")) +#undef REQUIRED_EXTENSIONS + +// SM3 +#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD | AARCH64_FL_SM4) +DEF_NEON_FUNCTION (vsm3ss1q, s_unsigned, ("Q0,Q0,Q0,Q0")) +DEF_NEON_FUNCTION (vsm3tt1aq, s_unsigned, ("Q0,Q0,Q0,Q0,s0", range<3, 0, 3>)) +DEF_NEON_FUNCTION (vsm3tt1bq, s_unsigned, ("Q0,Q0,Q0,Q0,s0", range<3, 0, 3>)) +DEF_NEON_FUNCTION (vsm3tt2aq, s_unsigned, ("Q0,Q0,Q0,Q0,s0", range<3, 0, 3>)) +DEF_NEON_FUNCTION (vsm3tt2bq, s_unsigned, ("Q0,Q0,Q0,Q0,s0", range<3, 0, 3>)) +DEF_NEON_FUNCTION (vsm3partw1q, s_unsigned, ("Q0,Q0,Q0,Q0")) +DEF_NEON_FUNCTION (vsm3partw2q, s_unsigned, ("Q0,Q0,Q0,Q0")) +#undef REQUIRED_EXTENSIONS + +// SM4 +#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD | AARCH64_FL_SM4) +DEF_NEON_FUNCTION (vsm4eq, s_unsigned, ("Q0,Q0,Q0")) +DEF_NEON_FUNCTION (vsm4ekeyq, s_unsigned, ("Q0,Q0,Q0")) #undef REQUIRED_EXTENSIONS \ No newline at end of file diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index d6ca018c7e88..0df54066b7a9 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -831,21 +831,6 @@ BUILTIN_GPI (UNOPUS, fixuns_truncsf, 2, FP) BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2, FP) - /* Implemented by aarch64_sm3ss1qv4si. */ - VAR1 (TERNOPU, sm3ss1q, 0, DEFAULT, v4si) - /* Implemented by aarch64_sm3tt<sm3tt_op>qv4si. */ - VAR1 (QUADOPUI, sm3tt1aq, 0, DEFAULT, v4si) - VAR1 (QUADOPUI, sm3tt1bq, 0, DEFAULT, v4si) - VAR1 (QUADOPUI, sm3tt2aq, 0, DEFAULT, v4si) - VAR1 (QUADOPUI, sm3tt2bq, 0, DEFAULT, v4si) - /* Implemented by aarch64_sm3partw<sm3part_op>qv4si. */ - VAR1 (TERNOPU, sm3partw1q, 0, DEFAULT, v4si) - VAR1 (TERNOPU, sm3partw2q, 0, DEFAULT, v4si) - /* Implemented by aarch64_sm4eqv4si. */ - VAR1 (BINOPU, sm4eq, 0, DEFAULT, v4si) - /* Implemented by aarch64_sm4ekeyqv4si. */ - VAR1 (BINOPU, sm4ekeyq, 0, DEFAULT, v4si) - /* Implemented by aarch64_fml<f16mac1>l<f16quad>_low<mode>. */ VAR1 (TERNOP, fmlal_low, 0, FP, v2sf) VAR1 (TERNOP, fmlsl_low, 0, FP, v2sf) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index a9b325cebde4..49fce2751ff4 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -20868,73 +20868,6 @@ vdotq_laneq_s32 (int32x4_t __r, int8x16_t __a, int8x16_t __b, const int __index) } #pragma GCC pop_options -#pragma GCC push_options -#pragma GCC target ("+nothing+sm4") - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsm3ss1q_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c) -{ - return __builtin_aarch64_sm3ss1qv4si_uuuu (__a, __b, __c); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsm3tt1aq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c, const int __imm2) -{ - return __builtin_aarch64_sm3tt1aqv4si_uuuus (__a, __b, __c, __imm2); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsm3tt1bq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c, const int __imm2) -{ - return __builtin_aarch64_sm3tt1bqv4si_uuuus (__a, __b, __c, __imm2); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsm3tt2aq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c, const int __imm2) -{ - return __builtin_aarch64_sm3tt2aqv4si_uuuus (__a, __b, __c, __imm2); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsm3tt2bq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c, const int __imm2) -{ - return __builtin_aarch64_sm3tt2bqv4si_uuuus (__a, __b, __c, __imm2); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsm3partw1q_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c) -{ - return __builtin_aarch64_sm3partw1qv4si_uuuu (__a, __b, __c); -} -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsm3partw2q_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c) -{ - return __builtin_aarch64_sm3partw2qv4si_uuuu (__a, __b, __c); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsm4eq_u32 (uint32x4_t __a, uint32x4_t __b) -{ - return __builtin_aarch64_sm4eqv4si_uuu (__a, __b); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsm4ekeyq_u32 (uint32x4_t __a, uint32x4_t __b) -{ - return __builtin_aarch64_sm4ekeyqv4si_uuu (__a, __b); -} - -#pragma GCC pop_options - #pragma GCC push_options #pragma GCC target ("+nothing+sha3") diff --git a/gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h b/gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h index 413c4021058e..fe90b124cc7b 100644 --- a/gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h +++ b/gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h @@ -1,6 +1,6 @@ #include "arm_neon.h" -#pragma GCC target "+simd+fp16+bf16+sha2+sha3+aes" +#pragma GCC target "+simd+fp16+bf16+sha2+sha3+aes+sm4" #define VEC_LEN(VEC) (sizeof (VEC) / sizeof (VEC[0])) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vsm3.c b/gcc/testsuite/gcc.target/aarch64/neon/vsm3.c new file mode 100644 index 000000000000..1eaee55a950e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vsm3.c @@ -0,0 +1,81 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vsm3ss1q_u32: +** sm3ss1 v0\.4s, v0\.4s, v1\.4s, v2\.4s +** ret +*/ +uint32x4_t +test_vsm3ss1q_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c) +{ + return vsm3ss1q_u32 (a, b, c); +} + +/* +** test_vsm3tt1aq_u32: +** sm3tt1a v0\.4s, v1\.4s, v2\.4s\[0\] +** ret +*/ +uint32x4_t +test_vsm3tt1aq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c) +{ + return vsm3tt1aq_u32 (a, b, c, 0); +} + +/* +** test_vsm3tt2bq_u32: +** sm3tt2b v0\.4s, v1\.4s, v2\.4s\[0\] +** ret +*/ +uint32x4_t +test_vsm3tt1bq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c) +{ + return vsm3tt1bq_u32 (a, b, c, 0); +} + +/* +** test_vsm3tt2aq_u32: +** sm3tt2a v0\.4s, v1\.4s, v2\.4s\[0\] +** ret +*/ +uint32x4_t +test_vsm3tt2aq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c) +{ + return vsm3tt2aq_u32 (a, b, c, 0); +} + +/* +** test_vsm3tt2bq_u32: +** sm3tt2b v0\.4s, v1\.4s, v2\.4s\[0\] +** ret +*/ +uint32x4_t +test_vsm3tt2bq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c) +{ + return vsm3tt2bq_u32 (a, b, c, 0); +} + +/* +** test_vsm3partw1q_u32: +** sm3partw1 v0\.4s, v1\.4s, v2\.4s +** ret +*/ +uint32x4_t +test_vsm3partw1q_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c) +{ + return vsm3partw1q_u32 (a, b, c); +} + +/* +** test_vsm3partw2q_u32: +** sm3partw2 v0\.4s, v1\.4s, v2\.4s +** ret +*/ +uint32x4_t +test_vsm3partw2q_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c) +{ + return vsm3partw2q_u32 (a, b, c); +} diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vsm4.c b/gcc/testsuite/gcc.target/aarch64/neon/vsm4.c new file mode 100644 index 000000000000..7d5481bede9c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vsm4.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vsm4eq_u32: +** sm4e v0\.4s, v1\.4s +** ret +*/ +uint32x4_t +test_vsm4eq_u32 (uint32x4_t a, uint32x4_t b) +{ + return vsm4eq_u32 (a, b); +} + +/* +** test_vsm4ekeyq_u32: +** sm4ekey v0\.4s, v0\.4s, v1\.4s +** ret +*/ +uint32x4_t +test_vsm4ekeyq_u32 (uint32x4_t a, uint32x4_t b) +{ + return vsm4ekeyq_u32 (a, b); +}
