https://gcc.gnu.org/g:e3ba6d338c766dfe7ca38c1df3a7f48113852616
commit r17-4796-ge3ba6d338c766dfe7ca38c1df3a7f48113852616 Author: Karl Meakin <[email protected]> Date: Thu Sep 24 17:19:14 2026 +0000 aarch64: Port NEON SHA1 intrinsics to pragma-based framework Port the SHA1 intrinsics (FEAT_SHA2) to the pragma-based framework and add assembly tests for each intrinsic. gcc/ChangeLog: * config/aarch64/aarch64-neon-builtins-base.cc: New function bases. * config/aarch64/aarch64-neon-builtins-base.def (vsha1cq, vsha1mq, vsha1pq, vsha1h, vsha1su0q, vsha1su1q): New function declarations. * config/aarch64/aarch64-simd-builtins.def: Delete builtin functions. * config/aarch64/arm_neon.h (vsha1cq_u32, vsha1mq_u32, vsha1pq_u32, vsha1h_u32, vsha1su0q_u32, vsha1su1q_u32): Delete function definitions gcc/testsuite/ChangeLog: * gcc.target/aarch64/neon/vsha1.c: New test. * gcc.target/aarch64/neon/arm_neon_test.h: Set `+sha2` target flag. Diff: --- gcc/config/aarch64/aarch64-neon-builtins-base.cc | 8 ++++ gcc/config/aarch64/aarch64-neon-builtins-base.def | 10 +++++ gcc/config/aarch64/aarch64-simd-builtins.def | 8 ---- gcc/config/aarch64/arm_neon.h | 42 ------------------ .../gcc.target/aarch64/neon/arm_neon_test.h | 2 +- gcc/testsuite/gcc.target/aarch64/neon/vsha1.c | 51 ++++++++++++++++++++++ 6 files changed, 70 insertions(+), 51 deletions(-) diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.cc b/gcc/config/aarch64/aarch64-neon-builtins-base.cc index 1bf4bf33d412..ef128d0de1df 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.cc @@ -797,4 +797,12 @@ NEON_FUNCTION (vaeseq, gimple_exact_insn<CODE_FOR_aarch64_crypto_aesev16qi>,) NEON_FUNCTION (vaesdq, gimple_exact_insn<CODE_FOR_aarch64_crypto_aesdv16qi>,) NEON_FUNCTION (vaesmcq, gimple_exact_insn<CODE_FOR_aarch64_crypto_aesmcv16qi>,) NEON_FUNCTION (vaesimcq, gimple_exact_insn<CODE_FOR_aarch64_crypto_aesimcv16qi>,) + +// SHA1 +NEON_FUNCTION (vsha1cq, gimple_exact_insn<CODE_FOR_aarch64_crypto_sha1cv4si>,) +NEON_FUNCTION (vsha1mq, gimple_exact_insn<CODE_FOR_aarch64_crypto_sha1mv4si>,) +NEON_FUNCTION (vsha1pq, gimple_exact_insn<CODE_FOR_aarch64_crypto_sha1pv4si>,) +NEON_FUNCTION (vsha1h, gimple_exact_insn<CODE_FOR_aarch64_crypto_sha1hsi>,) +NEON_FUNCTION (vsha1su0q, gimple_exact_insn<CODE_FOR_aarch64_crypto_sha1su0v4si>,) +NEON_FUNCTION (vsha1su1q, gimple_exact_insn<CODE_FOR_aarch64_crypto_sha1su1v4si>,) } diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.def b/gcc/config/aarch64/aarch64-neon-builtins-base.def index 57d4aa6dfffb..b0cc6d1ce92a 100644 --- a/gcc/config/aarch64/aarch64-neon-builtins-base.def +++ b/gcc/config/aarch64/aarch64-neon-builtins-base.def @@ -153,3 +153,13 @@ DEF_NEON_FUNCTION (vaesdq, b_unsigned, ("Q0,Q0,Q0")) DEF_NEON_FUNCTION (vaesmcq, b_unsigned, ("Q0,Q0")) DEF_NEON_FUNCTION (vaesimcq, b_unsigned, ("Q0,Q0")) #undef REQUIRED_EXTENSIONS + +// SHA1 +#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD | AARCH64_FL_SHA2) +DEF_NEON_FUNCTION (vsha1cq, s_unsigned, ("Q0,Q0,s0,Q0")) +DEF_NEON_FUNCTION (vsha1mq, s_unsigned, ("Q0,Q0,s0,Q0")) +DEF_NEON_FUNCTION (vsha1pq, s_unsigned, ("Q0,Q0,s0,Q0")) +DEF_NEON_FUNCTION (vsha1h, s_unsigned, ("s0,s0")) +DEF_NEON_FUNCTION (vsha1su0q, s_unsigned, ("Q0,Q0,Q0,Q0")) +DEF_NEON_FUNCTION (vsha1su1q, s_unsigned, ("Q0,Q0,Q0")) +#undef REQUIRED_EXTENSIONS \ No newline at end of file diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 5ee19ba0cd0d..11d418a68a4c 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -712,14 +712,6 @@ BUILTIN_VDQSF (QUADOP_LANE, float_mla_laneq, 0, FP) BUILTIN_VDQSF (QUADOP_LANE, float_mls_laneq, 0, FP) - /* Implemented by aarch64_crypto_sha1<op><mode>. */ - VAR1 (UNOPU, crypto_sha1h, 0, DEFAULT, si) - VAR1 (BINOPU, crypto_sha1su1, 0, DEFAULT, v4si) - VAR1 (TERNOPU, crypto_sha1c, 0, DEFAULT, v4si) - VAR1 (TERNOPU, crypto_sha1m, 0, DEFAULT, v4si) - VAR1 (TERNOPU, crypto_sha1p, 0, DEFAULT, v4si) - VAR1 (TERNOPU, crypto_sha1su0, 0, DEFAULT, v4si) - /* Implemented by aarch64_crypto_sha256<op><mode>. */ VAR1 (TERNOPU, crypto_sha256h, 0, DEFAULT, v4si) VAR1 (TERNOPU, crypto_sha256h2, 0, DEFAULT, v4si) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 38e33eef8137..b851f046bcb0 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -16728,48 +16728,6 @@ vrsrad_n_u64 (uint64_t __a, uint64_t __b, const int __c) /* vsha1 */ -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsha1cq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk) -{ - return __builtin_aarch64_crypto_sha1cv4si_uuuu (__hash_abcd, __hash_e, __wk); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsha1mq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk) -{ - return __builtin_aarch64_crypto_sha1mv4si_uuuu (__hash_abcd, __hash_e, __wk); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsha1pq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk) -{ - return __builtin_aarch64_crypto_sha1pv4si_uuuu (__hash_abcd, __hash_e, __wk); -} - -__extension__ extern __inline uint32_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsha1h_u32 (uint32_t __hash_e) -{ - return __builtin_aarch64_crypto_sha1hsi_uu (__hash_e); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsha1su0q_u32 (uint32x4_t __w0_3, uint32x4_t __w4_7, uint32x4_t __w8_11) -{ - return __builtin_aarch64_crypto_sha1su0v4si_uuuu (__w0_3, __w4_7, __w8_11); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vsha1su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w12_15) -{ - return __builtin_aarch64_crypto_sha1su1v4si_uuu (__tw0_3, __w12_15); -} - __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vsha256hq_u32 (uint32x4_t __hash_abcd, uint32x4_t __hash_efgh, uint32x4_t __wk) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h b/gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h index 856e1a081908..413c4021058e 100644 --- a/gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h +++ b/gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h @@ -1,6 +1,6 @@ #include "arm_neon.h" -#pragma GCC target "+simd+fp16+bf16+sha3+aes" +#pragma GCC target "+simd+fp16+bf16+sha2+sha3+aes" #define VEC_LEN(VEC) (sizeof (VEC) / sizeof (VEC[0])) diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vsha1.c b/gcc/testsuite/gcc.target/aarch64/neon/vsha1.c new file mode 100644 index 000000000000..a7d299feb367 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon/vsha1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon_test.h" + +/* +** test_vsha1cq_u32: +** fmov s([0-9]+), w0 +** sha1c q0, s\1, v1\.4s +** ret +*/ +TEST_TERNARY (vsha1cq_u32, uint32x4_t, uint32x4_t, uint32_t, uint32x4_t) + +/* +** test_vsha1mq_u32: +** fmov s([0-9]+), w0 +** sha1m q0, s\1, v1\.4s +** ret +*/ +TEST_TERNARY (vsha1mq_u32, uint32x4_t, uint32x4_t, uint32_t, uint32x4_t) + +/* +** test_vsha1pq_u32: +** fmov s([0-9]+), w0 +** sha1p q0, s\1, v1\.4s +** ret +*/ +TEST_TERNARY (vsha1pq_u32, uint32x4_t, uint32x4_t, uint32_t, uint32x4_t) + +/* +** test_vsha1h_u32: +** fmov s([0-9]+), w0 +** sha1h s\1, s\1 +** fmov w0, s\1 +** ret +*/ +TEST_UNARY (vsha1h_u32, uint32_t, uint32_t) + +/* +** test_vsha1su0q_u32: +** sha1su0 v0\.4s, v1\.4s, v2\.4s +** ret +*/ +TEST_UNIFORM_TERNARY (vsha1su0q_u32, uint32x4_t) + +/* +** test_vsha1su1q_u32: +** sha1su1 v0\.4s, v1\.4s +** ret +*/ +TEST_UNIFORM_BINARY (vsha1su1q_u32, uint32x4_t)
