https://gcc.gnu.org/g:eb37eb6bf47acc0b08e998de9d7517cbba648166
commit r17-4956-geb37eb6bf47acc0b08e998de9d7517cbba648166 Author: Jeevitha <[email protected]> Date: Wed Oct 7 07:34:54 2026 -0500 rs6000: Extend vcond_mask to cover V1TI [PR125060] The vcond_mask_<mode><mode> expander used the VEC_I mode iterator, while the vec_cmp<mode><mode> and vec_cmpu<mode><mode> expanders already used VEC_IC, which includes V1TI for Power10. As a result, vcond_mask_v1tiv1ti was not generated for V1TI. Without vcond_mask_v1tiv1ti, expand_vec_cond_expr_p returns false for V1TI and veclower2 scalarises the VEC_COND_EXPR for vector __int128 comparisons through GPRs, losing the xxlnor instructions expected by fold-vec-cmp-int128.c and pr103316.c. Fix this by changing the iterator for vcond_mask_<mode><mode> from VEC_I to VEC_IC. 2026-10-07 Jeevitha Palanisamy <[email protected]> gcc/ PR target/125060 * config/rs6000/vector.md (vcond_mask_<mode><mode>): Change the mode iterator from VEC_I to VEC_IC to support V1TI. Diff: --- gcc/config/rs6000/vector.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 22eee2f81f05..7a44a8a7e553 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -336,10 +336,10 @@ ;; Same mode for condition true/false values and predicate operand. (define_expand "vcond_mask_<mode><mode>" - [(match_operand:VEC_I 0 "vint_operand") - (match_operand:VEC_I 1 "vint_operand") - (match_operand:VEC_I 2 "vint_operand") - (match_operand:VEC_I 3 "vint_operand")] + [(match_operand:VEC_IC 0 "vint_operand") + (match_operand:VEC_IC 1 "vint_operand") + (match_operand:VEC_IC 2 "vint_operand") + (match_operand:VEC_IC 3 "vint_operand")] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" { emit_insn (gen_vector_select_<mode> (operands[0], operands[2], operands[1],
