https://gcc.gnu.org/g:06cee27b6943fdfe6082dbee4c260b2efe22a193
commit r17-5069-g06cee27b6943fdfe6082dbee4c260b2efe22a193 Author: Jeff Law <[email protected]> Date: Sun Oct 11 12:29:52 2026 -0600 [RISC-V] Remove obsolete, never taken to silicon xventanacondops extension This patch removes the xventanacondops support from GCC. It was something I meant to do last cycle, but never got around to it. xventanacondops was specific to the first generation Ventana design which we ultimately decided to shelve for various reasons. It was never taken to silicon by anyone. zicond provides the exact same functionality, but is standardized by RVI and naturally sits in a different encoding space. I'm keen to avoid keeping around code which will never be used. Given the design never made it to silicon, I don't really even see the point in keeping the options lying around for compatibility purposes. As a result this is a complete removal. Tested on riscv32-elf and riscv64-elf. Bootstraps on the various designs will happen tonight as part of the regular cycle. gcc/ * config/riscv/predicates.md (movcc_operand): Replace TARGET_ZICOND_LIKE with TARGET_ZICOND. * config/riscv/riscv.cc (riscv_rtx_costs): Likewise. (riscv_expand_conditional_move): Likewise. * config/riscv/riscv-ext-ventana.def: Remove. * config/riscv/riscv-ext.def: Don't include riscv-ext_ventana.def. * config/riscv/riscv-ext.opt: Regenerated. * config/riscv/riscv-opts.h (TARGET_ZICOND_LIKE): Remove. * config/riscv/riscv.md: Remove references to XVentanacondops. Replace TARGET_ZICOND_LIKE with TARGET_ZICOND. * config/riscv/t-riscv (RISCV_EXT_DEFS): Remove riscv-ext-ventana.def. * config/riscv/zicond.md: Remove references to XVentanaCondOps. Replace TARGET_ZICOND_LIKE with TARGET_ZICOND throughout. Simplify where possible. * doc/riscv-ext.texi: Regenerated. gcc/testsuite/ * gcc.target/riscv/cset-sext-ventana-rtl.c: Remove. * gcc.target/riscv/cset-sext-ventana.c: Remove. * gcc.target/riscv/movdibeq-ventana.c: Remove. * gcc.target/riscv/movdibfeq-ventana.c: Remove. * gcc.target/riscv/movdibfge-ventana.c: Remove. * gcc.target/riscv/movdibfgt-ventana.c: Remove. * gcc.target/riscv/movdibfle-ventana.c: Remove. * gcc.target/riscv/movdibflt-ventana.c: Remove. * gcc.target/riscv/movdibfne-ventana.c: Remove. * gcc.target/riscv/movdibge-ventana.c: Remove. * gcc.target/riscv/movdibgeu-ventana.c: Remove. * gcc.target/riscv/movdibgt-ventana.c: Remove. * gcc.target/riscv/movdibgtu-ventana.c: Remove. * gcc.target/riscv/movdible-ventana.c: Remove. * gcc.target/riscv/movdibleu-ventana.c: Remove. * gcc.target/riscv/movdiblt-ventana.c: Remove. * gcc.target/riscv/movdibltu-ventana.c: Remove. * gcc.target/riscv/movdibne-ventana.c: Remove. * gcc.target/riscv/movdieq-ventana.c: Remove. * gcc.target/riscv/movdifeq-ventana.c: Remove. * gcc.target/riscv/movdifge-ventana.c: Remove. * gcc.target/riscv/movdifgt-ventana.c: Remove. * gcc.target/riscv/movdifle-ventana.c: Remove. * gcc.target/riscv/movdiflt-ventana.c: Remove. * gcc.target/riscv/movdifne-ventana.c: Remove. * gcc.target/riscv/movdige-ventana.c: Remove. * gcc.target/riscv/movdigeu-ventana.c: Remove. * gcc.target/riscv/movdigt-ventana.c: Remove. * gcc.target/riscv/movdigtu-ventana.c: Remove. * gcc.target/riscv/movdile-ventana.c: Remove. * gcc.target/riscv/movdileu-ventana.c: Remove. * gcc.target/riscv/movdilt-ventana.c: Remove. * gcc.target/riscv/movdiltu-ventana.c: Remove. * gcc.target/riscv/movdine-ventana.c: Remove. * gcc.target/riscv/movsibeq-ventana.c: Remove. * gcc.target/riscv/movsibfeq-ventana.c: Remove. * gcc.target/riscv/movsibfge-ventana.c: Remove. * gcc.target/riscv/movsibfgt-ventana.c: Remove. * gcc.target/riscv/movsibfle-ventana.c: Remove. * gcc.target/riscv/movsibflt-ventana.c: Remove. * gcc.target/riscv/movsibfne-ventana.c: Remove. * gcc.target/riscv/movsibge-ventana.c: Remove. * gcc.target/riscv/movsibgeu-ventana.c: Remove. * gcc.target/riscv/movsibgt-ventana.c: Remove. * gcc.target/riscv/movsibgtu-ventana.c: Remove. * gcc.target/riscv/movsible-ventana.c: Remove. * gcc.target/riscv/movsibleu-ventana.c: Remove. * gcc.target/riscv/movsiblt-ventana.c: Remove. * gcc.target/riscv/movsibltu-ventana.c: Remove. * gcc.target/riscv/movsibne-ventana.c: Remove. * gcc.target/riscv/movsieq-ventana.c: Remove. * gcc.target/riscv/movsifeq-ventana.c: Remove. * gcc.target/riscv/movsifge-ventana.c: Remove. * gcc.target/riscv/movsifgt-ventana.c: Remove. * gcc.target/riscv/movsifle-ventana.c: Remove. * gcc.target/riscv/movsiflt-ventana.c: Remove. * gcc.target/riscv/movsifne-ventana.c: Remove. * gcc.target/riscv/movsige-ventana.c: Remove. * gcc.target/riscv/movsigeu-ventana.c: Remove. * gcc.target/riscv/movsigt-ventana.c: Remove. * gcc.target/riscv/movsigtu-ventana.c: Remove. * gcc.target/riscv/movsile-ventana.c: Remove. * gcc.target/riscv/movsileu-ventana.c: Remove. * gcc.target/riscv/movsilt-ventana.c: Remove. * gcc.target/riscv/movsiltu-ventana.c: Remove. * gcc.target/riscv/movsine-ventana.c: Remove. * gcc.target/riscv/predef-30.c: Remove. * gcc.target/riscv/ventana-16122.c: Remove. * gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: Remove. * gcc.target/riscv/xventanacondops-primitiveSemantics.c: Remove. * gcc.target/riscv/xventanacondops-xor-01.c: Remove. * gcc.target/riscv/pr116240.c: Change xventanacondops to zicond. Diff: --- gcc/config/riscv/predicates.md | 2 +- gcc/config/riscv/riscv-ext-ventana.def | 35 --------- gcc/config/riscv/riscv-ext.def | 1 - gcc/config/riscv/riscv-ext.opt | 5 -- gcc/config/riscv/riscv-opts.h | 2 - gcc/config/riscv/riscv.cc | 10 +-- gcc/config/riscv/riscv.md | 6 +- gcc/config/riscv/t-riscv | 1 - gcc/config/riscv/zicond.md | 83 +++++++-------------- gcc/doc/riscv-ext.texi | 4 - .../gcc.target/riscv/cset-sext-ventana-rtl.c | 86 ---------------------- gcc/testsuite/gcc.target/riscv/cset-sext-ventana.c | 25 ------- gcc/testsuite/gcc.target/riscv/movdibeq-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdibfeq-ventana.c | 30 -------- gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c | 29 -------- gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c | 30 -------- gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c | 30 -------- gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c | 30 -------- gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c | 30 -------- gcc/testsuite/gcc.target/riscv/movdibge-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdibgeu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdibgt-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdibgtu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdible-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdibleu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdiblt-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdibltu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdibne-ventana.c | 30 -------- gcc/testsuite/gcc.target/riscv/movdieq-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdifeq-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdifge-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdifgt-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdifle-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdiflt-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdifne-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdige-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdigeu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdigt-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdigtu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdile-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdileu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdilt-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdiltu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movdine-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsibeq-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsibfeq-ventana.c | 30 -------- gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c | 30 -------- gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c | 30 -------- gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c | 30 -------- gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c | 30 -------- gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c | 30 -------- gcc/testsuite/gcc.target/riscv/movsibge-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsibgeu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsibgt-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsibgtu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsible-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsibleu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsiblt-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsibltu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsibne-ventana.c | 30 -------- gcc/testsuite/gcc.target/riscv/movsieq-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsifeq-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsifge-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsifgt-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsifle-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsiflt-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsifne-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsige-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsigeu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsigt-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsigtu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsile-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsileu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsilt-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsiltu-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/movsine-ventana.c | 28 ------- gcc/testsuite/gcc.target/riscv/pr116240.c | 2 +- gcc/testsuite/gcc.target/riscv/predef-30.c | 27 ------- gcc/testsuite/gcc.target/riscv/ventana-16122.c | 19 ----- .../xventanacondops-primitiveSemantics-rv32.c | 8 -- .../riscv/xventanacondops-primitiveSemantics.c | 10 --- .../gcc.target/riscv/xventanacondops-xor-01.c | 8 -- 82 files changed, 36 insertions(+), 2117 deletions(-) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 3ee9042b949c..17ca8ef093a6 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -67,7 +67,7 @@ (define_predicate "movcc_operand" (if_then_else (match_test "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV - || TARGET_ZICOND_LIKE") + || TARGET_ZICOND") (match_operand 0 "sfb_alu_operand") (match_operand 0 "arith_operand"))) diff --git a/gcc/config/riscv/riscv-ext-ventana.def b/gcc/config/riscv/riscv-ext-ventana.def deleted file mode 100644 index 2fd085bd2ac3..000000000000 --- a/gcc/config/riscv/riscv-ext-ventana.def +++ /dev/null @@ -1,35 +0,0 @@ -/* Ventana extension definition file for RISC-V. - Copyright (C) 2025-2026 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. - -Please run `make riscv-regen` in build folder to make sure updated anything. - -Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ - -DEFINE_RISCV_EXT( - /* NAME */ xventanacondops, - /* UPPERCASE_NAME */ XVENTANACONDOPS, - /* FULL_NAME */ "Ventana integer conditional operations extension", - /* DESC */ "", - /* URL */ , - /* DEP_EXTS */ ({}), - /* SUPPORTED_VERSIONS */ ({{1, 0}}), - /* FLAG_GROUP */ xventana, - /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, - /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, - /* EXTRA_EXTENSION_FLAGS */ 0) diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def index eeee99da77e2..847c6e07b649 100644 --- a/gcc/config/riscv/riscv-ext.def +++ b/gcc/config/riscv/riscv-ext.def @@ -2229,7 +2229,6 @@ DEFINE_RISCV_EXT( #include "riscv-ext-corev.def" #include "riscv-ext-sifive.def" #include "riscv-ext-thead.def" -#include "riscv-ext-ventana.def" #include "riscv-ext-mips.def" #include "riscv-ext-andes.def" #include "riscv-ext-spacemit.def" diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt index 8cd7825522b3..9ed0f433c874 100644 --- a/gcc/config/riscv/riscv-ext.opt +++ b/gcc/config/riscv/riscv-ext.opt @@ -61,9 +61,6 @@ int riscv_xsmt_subext TargetVariable int riscv_xthead_subext -TargetVariable -int riscv_xventana_subext - TargetVariable int riscv_za_subext @@ -477,8 +474,6 @@ Mask(XTHEADSYNC) Var(riscv_xthead_subext) Mask(XTHEADVECTOR) Var(riscv_xthead_subext) -Mask(XVENTANACONDOPS) Var(riscv_xventana_subext) - Mask(XMIPSCMOV) Var(riscv_xmips_subext) Mask(XMIPSCBOP) Var(riscv_xmips_subext) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 25e827e9fb52..8711031d7093 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -159,8 +159,6 @@ enum rvv_vector_bits_enum { RVV_VECTOR_BITS_ZVL, }; -#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT)) - /* Bit of riscv_zvl_flags will set continually, N-1 bit will set if N-bit is set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use popcount to calculate the minimal VLEN. */ diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index bf1290317f3b..e910245c2bcc 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4679,7 +4679,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = COSTS_N_INSNS (1); return true; } - else if (TARGET_ZICOND_LIKE + else if (TARGET_ZICOND && outer_code == SET && ((GET_CODE (XEXP (x, 1)) == REG && XEXP (x, 2) == CONST0_RTX (GET_MODE (XEXP (x, 1)))) @@ -6447,7 +6447,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) } - if (((TARGET_ZICOND_LIKE + if (((TARGET_ZICOND || (arith_operand (cons, dst_mode) && arith_operand (alt, dst_mode))) && GET_MODE_CLASS (dst_mode) == MODE_INT && GET_MODE_CLASS (cond_mode) == MODE_INT) @@ -6460,7 +6460,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) for the output of the SCC instruction, to match the mode of the NEG operation below. The output of SCC is 0 or 1 boolean, so it is valid for input in any scalar integer mode. */ - rtx tmp = gen_reg_rtx ((TARGET_ZICOND_LIKE || TARGET_COND_MOV) + rtx tmp = gen_reg_rtx ((TARGET_ZICOND || TARGET_COND_MOV) ? word_mode : dst_mode); bool invert = false; @@ -6533,13 +6533,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) op0 = XEXP (op, 0); op1 = XEXP (op, 1); } - else if (!TARGET_ZICOND_LIKE && !TARGET_COND_MOV) + else if (!TARGET_ZICOND && !TARGET_COND_MOV) riscv_expand_int_scc (tmp, code, op0, op1, &invert); if (TARGET_COND_MOV) return riscv_target_conditional_move (dest, op0, op1, code, cons, alt); - else if (!TARGET_ZICOND_LIKE) + else if (!TARGET_ZICOND) { if (invert) std::swap (cons, alt); diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index e70439f5a0de..51e16c5e9810 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3214,7 +3214,7 @@ ;; Canonical form for an extend of a logical shift right (sign/zero extraction). ;; Special cases, that are ignored (handled elsewhere): ;; * Single-bit extraction (Zbs/XTheadBs) -;; * Single-bit extraction (Zicondops/XVentanaCondops) +;; * Single-bit extraction (Zicondops) ;; * Single-bit extraction (SFB) ;; * Extraction instruction th.ext(u) (XTheadBb) ;; * lshrsi3_extend_2 (see above) @@ -3225,7 +3225,7 @@ (match_operand 2 "const_int_operand") (match_operand 3 "const_int_operand")))] "!((TARGET_ZBS || TARGET_XTHEADBS || TARGET_ZICOND - || TARGET_XVENTANACONDOPS || TARGET_SFB_ALU) + || TARGET_SFB_ALU) && (INTVAL (operands[2]) == 1)) && !TARGET_XTHEADBB && !TARGET_XANDESPERF @@ -3507,7 +3507,7 @@ (if_then_else:GPR (match_operand 1 "comparison_operator") (match_operand:GPR 2 "movcc_operand") (match_operand:GPR 3 "movcc_operand")))] - "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND_LIKE + "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND || TARGET_MOVCC || TARGET_XMIPSCMOV" { if (riscv_expand_conditional_move (operands[0], operands[1], diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv index 2a4a2ccab505..cdf2f87128ab 100644 --- a/gcc/config/riscv/t-riscv +++ b/gcc/config/riscv/t-riscv @@ -223,7 +223,6 @@ RISCV_EXT_DEFS = \ $(srcdir)/config/riscv/riscv-ext.def \ $(srcdir)/config/riscv/riscv-ext-sifive.def \ $(srcdir)/config/riscv/riscv-ext-thead.def \ - $(srcdir)/config/riscv/riscv-ext-ventana.def \ $(srcdir)/config/riscv/riscv-ext-mips.def \ $(srcdir)/config/riscv/riscv-ext-andes.def \ $(srcdir)/config/riscv/riscv-ext-spacemit.def diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index a69f55e82d18..99a8a4abf5b0 100644 --- a/gcc/config/riscv/zicond.md +++ b/gcc/config/riscv/zicond.md @@ -1,5 +1,4 @@ -;; Machine description for the RISC-V Zicond extension and functionally- -;; equivalent XVentanaCondOps vendor extension +;; Machine description for the RISC-V Zicond extension ;; Copyright (C) 2022-2026 Free Software Foundation, Inc. ;; This file is part of GCC. @@ -21,25 +20,16 @@ (define_code_iterator eq_or_ne [eq ne]) (define_code_attr eqz [(eq "nez") (ne "eqz")]) (define_code_attr nez [(eq "eqz") (ne "nez")]) -(define_code_attr eqz_ventana [(eq "n") (ne "")]) -(define_code_attr nez_ventana [(eq "") (ne "n")]) -;; Zicond / XVentanaCondOps +;; Zicond (define_insn "*czero.<eqz>.<GPR:mode><X:mode>" [(set (match_operand:GPR 0 "register_operand" "=r") (if_then_else:GPR (eq_or_ne (match_operand:X 1 "register_operand" "r") (const_int 0)) (match_operand:GPR 2 "register_operand" "r") (const_int 0)))] - "TARGET_ZICOND_LIKE" - { - if (TARGET_ZICOND) - return "czero.<eqz>\t%0,%2,%1"; - else if (TARGET_XVENTANACONDOPS && TARGET_64BIT) - return "vt.maskc<eqz_ventana>\t%0,%2,%1"; - else - gcc_unreachable (); - } + "TARGET_ZICOND" + "czero.<eqz>\t%0,%2,%1" [(set_attr "type" "zicond")]) (define_insn "*czero.<nez>.<GPR:mode><X:mode>" @@ -48,15 +38,8 @@ (const_int 0)) (const_int 0) (match_operand:GPR 2 "register_operand" "r")))] - "TARGET_ZICOND_LIKE" - { - if (TARGET_ZICOND) - return "czero.<nez>\t%0,%2,%1"; - else if (TARGET_XVENTANACONDOPS && TARGET_64BIT) - return "vt.maskc<nez_ventana>\t%0,%2,%1"; - else - gcc_unreachable (); - } + "TARGET_ZICOND" + "czero.<nez>\t%0,%2,%1" [(set_attr "type" "zicond")]) ;; Special optimization under eq/ne in primitive semantics @@ -66,15 +49,8 @@ (const_int 0)) (match_operand:GPR 2 "register_operand" "1") (match_operand:GPR 3 "register_operand" "r")))] - "TARGET_ZICOND_LIKE && rtx_equal_p (operands[1], operands[2])" - { - if (TARGET_ZICOND) - return "czero.eqz\t%0,%3,%1"; - else if (TARGET_XVENTANACONDOPS && TARGET_64BIT) - return "vt.maskc\t%0,%3,%1"; - else - gcc_unreachable (); - } + "TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])" + "czero.eqz\t%0,%3,%1" [(set_attr "type" "zicond")]) (define_insn "*czero.nez.<GPR:mode><X:mode>.opt2" @@ -84,14 +60,7 @@ (match_operand:GPR 2 "register_operand" "r") (match_operand:GPR 3 "register_operand" "1")))] "TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])" - { - if (TARGET_ZICOND) - return "czero.eqz\t%0,%2,%1"; - else if (TARGET_XVENTANACONDOPS && TARGET_64BIT) - return "vt.maskc\t%0,%2,%1"; - else - gcc_unreachable (); - } + "czero.eqz\t%0,%2,%1"; [(set_attr "type" "zicond")]) ;; Combine creates this form in some cases (particularly the coremark @@ -103,7 +72,7 @@ (match_operand 2 "immediate_operand")) (match_operand:X 3 "register_operand"))) (clobber (match_operand:X 4 "register_operand"))] - "TARGET_ZICOND_LIKE && TARGET_ZBS" + "TARGET_ZICOND && TARGET_ZBS" [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) (set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0)) (const_int 0) @@ -116,7 +85,7 @@ (match_operand 2 "immediate_operand")) (match_operand:X 3 "register_operand"))) (clobber (match_operand:X 4 "register_operand"))] - "TARGET_ZICOND_LIKE && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)" + "TARGET_ZICOND && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)" [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2))) (set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0)) (const_int 0) @@ -137,7 +106,7 @@ (scc_0:X (match_operand:X 3 "register_operand") (match_operand:X 4 "reg_or_0_operand")))) (clobber (match_operand:X 5 "register_operand"))] - "TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV" + "TARGET_ZICOND || TARGET_XTHEADCONDMOV" [(set (match_dup 5) (scc_0:X (match_dup 3) (match_dup 4))) (set (match_dup 0) (if_then_else:X (match_op_dup 1 [(match_dup 2) (const_int 0)]) @@ -155,7 +124,7 @@ (match_operator:X 1 "equality_operator" [(match_operand:X 2 "register_operand") (const_int 0)]))) (clobber (match_operand:X 5 "register_operand"))] - "TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV" + "TARGET_ZICOND || TARGET_XTHEADCONDMOV" [(set (match_dup 5) (scc_0:X (match_dup 3) (match_dup 4))) (set (match_dup 0) (if_then_else:X (match_op_dup:X 1 [(match_dup 2) (const_int 0)]) @@ -175,7 +144,7 @@ (any_ge:X (match_operand:X 3 "register_operand") (const_int 1)))) (clobber (match_operand:X 4 "register_operand"))] - "TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV" + "TARGET_ZICOND || TARGET_XTHEADCONDMOV" [(set (match_dup 4) (any_ge:X (match_dup 3) (const_int 1))) (set (match_dup 0) (if_then_else:X (match_op_dup:X 1 [(match_dup 2) (const_int 0)]) @@ -193,7 +162,7 @@ (match_operator:X 1 "equality_operator" [(match_operand:X 2 "register_operand") (const_int 0)]))) (clobber (match_operand:X 4 "register_operand"))] - "TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV" + "TARGET_ZICOND || TARGET_XTHEADCONDMOV" [(set (match_dup 4) (any_ge:X (match_dup 3) (const_int 1))) (set (match_dup 0) (if_then_else:X (match_op_dup:X 1 [(match_dup 2) (const_int 0)]) @@ -212,7 +181,7 @@ (any_lt:X (match_operand:X 3 "register_operand") (match_operand:X 4 "arith_operand")))) (clobber (match_operand:X 5 "register_operand"))] - "TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV" + "TARGET_ZICOND || TARGET_XTHEADCONDMOV" [(set (match_dup 5) (any_lt:X (match_dup 3) (match_dup 4))) (set (match_dup 0) (if_then_else:X (match_op_dup:X 1 [(match_dup 2) (const_int 0)]) @@ -231,7 +200,7 @@ (any_le:X (match_operand:X 3 "register_operand") (match_operand:X 4 "sle_operand")))) (clobber (match_operand:X 5 "register_operand"))] - "TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV" + "TARGET_ZICOND || TARGET_XTHEADCONDMOV" [(set (match_dup 5) (any_le:X (match_dup 3) (match_dup 4))) (set (match_dup 0) (if_then_else:X (match_op_dup:X 1 [(match_dup 2) (const_int 0)]) @@ -253,7 +222,7 @@ (match_operand 2 "const_int_operand") (match_operand 3 "const_int_operand")) (match_operand 4 "const_int_operand")))] - "((TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV) + "((TARGET_ZICOND || TARGET_XTHEADCONDMOV) && INTVAL (operands[2]) + INTVAL (operands[4]) == 1 && INTVAL (operands[3]) + INTVAL (operands[4]) == -1)" [(set (match_dup 0) (ashiftrt:X (match_dup 1) (match_dup 2))) @@ -272,7 +241,7 @@ (match_operand 2 "const_int_operand") (match_operand 3 "const_int_operand")) (match_operand 4 "const_int_operand")))] - "((TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV) + "((TARGET_ZICOND || TARGET_XTHEADCONDMOV) && INTVAL (operands[2]) + INTVAL (operands[4]) == -1 && INTVAL (operands[3]) + INTVAL (operands[4]) == 1)" [(set (match_dup 0) (ashiftrt:X (match_dup 1) (match_dup 2))) @@ -321,7 +290,7 @@ (match_operand:X 3 "register_operand")) (const_int 0)))) (clobber (match_operand:X 4 "register_operand"))] - "TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV" + "TARGET_ZICOND || TARGET_XTHEADCONDMOV" [(set (match_dup 4) (if_then_else:X (ne:X (match_dup 1) (const_int 0)) (match_dup 3) (const_int 0))) @@ -340,7 +309,7 @@ (match_dup 2)) (const_int 0)))) (clobber (match_operand:X 4 "register_operand"))] - "TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV" + "TARGET_ZICOND || TARGET_XTHEADCONDMOV" [(set (match_dup 4) (if_then_else:X (ne:X (match_dup 1) (const_int 0)) (match_dup 3) (const_int 0))) @@ -362,7 +331,7 @@ (match_operand:QI 3 "register_operand")) (const_int 0)))) (clobber (match_operand:X 4 "register_operand"))] - "TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV" + "TARGET_ZICOND || TARGET_XTHEADCONDMOV" [(set (match_dup 4) (if_then_else:X (ne:X (match_dup 1) (const_int 0)) (match_dup 3) (const_int 0))) @@ -386,7 +355,7 @@ (match_dup 2) (match_operand:X 3 "register_operand" "r")) (const_int 0))))] - "(TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV) && can_create_pseudo_p ()" + "(TARGET_ZICOND || TARGET_XTHEADCONDMOV) && can_create_pseudo_p ()" "#" "&& 1" [(set (match_dup 4) (and:X (match_dup 2) (match_dup 3))) @@ -410,7 +379,7 @@ (match_operand:X 3 "register_operand" "r") (match_dup 2)) (const_int 0))))] - "(TARGET_ZICOND_LIKE || TARGET_XTHEADCONDMOV) && can_create_pseudo_p ()" + "(TARGET_ZICOND || TARGET_XTHEADCONDMOV) && can_create_pseudo_p ()" "#" "&& 1" [(set (match_dup 4) (and:X (match_dup 2) (match_dup 3))) @@ -495,7 +464,7 @@ (match_operand:X 2 "sle<u>_operand")) (match_operand:GPR 3 "register_operand") (const_int 0)))] - "TARGET_ZICOND_LIKE && can_create_pseudo_p ()" + "TARGET_ZICOND && can_create_pseudo_p ()" [(set (match_dup 4) (any_le:X (match_dup 1) (match_dup 2))) (set (match_dup 0) (if_then_else:GPR (ne:X (match_dup 4) (const_int 0)) @@ -512,7 +481,7 @@ (match_operand:X 2 "sle<u>_operand")) (match_operand:GPR 3 "register_operand") (const_int 0)))] - "TARGET_ZICOND_LIKE && can_create_pseudo_p ()" + "TARGET_ZICOND && can_create_pseudo_p ()" [(set (match_dup 4) (<gt_to_le>:X (match_dup 1) (match_dup 2))) (set (match_dup 0) (if_then_else:GPR (eq:X (match_dup 4) (const_int 0)) diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi index c3fc8c79118e..a930b8ed5fb8 100644 --- a/gcc/doc/riscv-ext.texi +++ b/gcc/doc/riscv-ext.texi @@ -754,10 +754,6 @@ @tab 1.0 @tab T-head vector extension -@item @samp{xventanacondops} -@tab 1.0 -@tab Ventana integer conditional operations extension - @item @samp{xmipscmov} @tab 1.0 @tab Mips conditional move extension diff --git a/gcc/testsuite/gcc.target/riscv/cset-sext-ventana-rtl.c b/gcc/testsuite/gcc.target/riscv/cset-sext-ventana-rtl.c deleted file mode 100644 index e2939c66ab0a..000000000000 --- a/gcc/testsuite/gcc.target/riscv/cset-sext-ventana-rtl.c +++ /dev/null @@ -1,86 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-flto" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -int __RTL (startwith ("ce1")) -foo (long a, long b) -{ -(function "foo" - (param "a" - (DECL_RTL (reg/v:DI <2> [ a ])) - (DECL_RTL_INCOMING (reg:DI a0 [ a ]))) - (param "b" - (DECL_RTL (reg/v:DI <3> [ b ])) - (DECL_RTL_INCOMING (reg:DI a1 [ b ]))) - (insn-chain - (block 2 - (edge-from entry (flags "FALLTHRU")) - (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK) - (cinsn 2 (set (reg/v:DI <2> [ a ]) - (reg:DI a0 [ a ])) "cset-sext-ventana.c":8:1 - (expr_list:REG_DEAD (reg:DI a0 [ a ]))) - (cinsn 3 (set (reg/v:DI <3> [ b ]) - (reg:DI a1 [ b ])) "cset-sext-ventana.c":8:1 - (expr_list:REG_DEAD (reg:DI a1 [ b ]))) - (cnote 4 NOTE_INSN_FUNCTION_BEG) - (cjump_insn 8 (set (pc) - (if_then_else (eq (reg/v:DI <3> [ b ]) - (const_int 0)) - (label_ref:DI 24) - (pc))) "cset-sext-ventana.c":9:6 - (expr_list:REG_DEAD (reg/v:DI <3> [ b ]) - (int_list:REG_BR_PROB 365072228))) - (edge-to 4) - (edge-to 3 (flags "FALLTHRU")) - ) ;; block 2 - (block 3 - (edge-from 2 (flags "FALLTHRU")) - (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK) - (cinsn 10 (set (reg:SI <5>) - (ne:SI (reg/v:DI <2> [ a ]) - (const_int 0))) "cset-sext-ventana.c":11:11 - (expr_list:REG_DEAD (reg/v:DI <2> [ a ]))) - (cinsn 11 (set (reg:DI <1> [ <retval> ]) - (sign_extend:DI (reg:SI <5>))) "cset-sext-ventana.c":11:11 - (expr_list:REG_DEAD (reg:SI <5>))) - (edge-to 5 (flags "FALLTHRU")) - ) ;; block 3 - (block 4 - (edge-from 2) - (clabel 24 3) - (cnote 23 [bb 4] NOTE_INSN_BASIC_BLOCK) - (cinsn 5 (set (reg:DI <1> [ <retval> ]) - (const_int 0)) "cset-sext-ventana.c":10:12) - (edge-to 5 (flags "FALLTHRU")) - ) ;; block 4 - (block 5 - (edge-from 4 (flags "FALLTHRU")) - (edge-from 3 (flags "FALLTHRU")) - (clabel 12 2) - (cnote 13 [bb 5] NOTE_INSN_BASIC_BLOCK) - (cinsn 18 (set (reg/i:DI a0) - (reg:DI <1> [ <retval> ])) "cset-sext-ventana.c":15:1 - (expr_list:REG_DEAD (reg:DI <1> [ <retval> ]))) - (cinsn 19 (use (reg/i:DI a0)) "cset-sext-ventana.c":15:1) - (edge-to exit (flags "FALLTHRU")) - ) ;; block 5 - ) ;; insn-chain - (crtl - (return_rtx - (reg/i:DI a0) - ) ;; return_rtx - ) ;; crtl -) ;; function "foo" -} - -/* Expect branchless assembly like: - - snez a0,a0 - vt.maskc a0,a0,a1 - */ - -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cset-sext-ventana.c b/gcc/testsuite/gcc.target/riscv/cset-sext-ventana.c deleted file mode 100644 index 4bb6be046fac..000000000000 --- a/gcc/testsuite/gcc.target/riscv/cset-sext-ventana.c +++ /dev/null @@ -1,25 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=1" } */ - -int -foo (long a, long b) -{ - if (!b) - return 0; - else if (a) - return 1; - else - return 0; -} - -/* Expect branchless assembly like: - - snez a0,a0 - vt.maskc a0,a0,a1 - */ - -/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibeq-ventana.c deleted file mode 100644 index 689297e19810..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibeq-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdieq (int_t w, int_t x, int_t y, int_t z) -{ - return w == x ? y : z; -} - -/* Expect branched assembly like: - - bne a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\ssub\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibfeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfeq-ventana.c deleted file mode 100644 index 2ea79443d5c5..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibfeq-ventana.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdifeq (double w, double x, int_t y, int_t z) -{ - return w == x ? y : z; -} - -/* Expect branched assembly like: - - feq.d a4,fa0,fa1 - mv a5,a0 - mv a0,a1 - beq a4,zero,.L2 - mv a0,a5 -.L2: - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c deleted file mode 100644 index 516a676a9da5..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c +++ /dev/null @@ -1,29 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdifge (double w, double x, int_t y, int_t z) -{ - return w >= x ? y : z; -} - -/* Expect branched assembly like: - - fge.d a4,fa0,fa1 - mv a5,a0 - mv a0,a1 - beq a4,zero,.L2 - mv a0,a5 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c deleted file mode 100644 index 92d55ecbdcb1..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdifgt (double w, double x, int_t y, int_t z) -{ - return w > x ? y : z; -} - -/* Expect branched assembly like: - - fgt.d a4,fa0,fa1 - mv a5,a0 - mv a0,a1 - beq a4,zero,.L2 - mv a0,a5 -.L2: - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c deleted file mode 100644 index bdddf6e953e3..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdifle (double w, double x, int_t y, int_t z) -{ - return w <= x ? y : z; -} - -/* Expect branched assembly like: - - fle.d a4,fa0,fa1 - mv a5,a0 - mv a0,a1 - beq a4,zero,.L2 - mv a0,a5 -.L2: - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c deleted file mode 100644 index 76ffc9cc56b8..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdiflt (double w, double x, int_t y, int_t z) -{ - return w < x ? y : z; -} - -/* Expect branched assembly like: - - flt.d a4,fa0,fa1 - mv a5,a0 - mv a0,a1 - beq a4,zero,.L2 - mv a0,a5 -.L2: - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c deleted file mode 100644 index d5408f9deece..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdifne (double w, double x, int_t y, int_t z) -{ - return w != x ? y : z; -} - -/* Expect branched assembly like: - - feq.d a4,fa0,fa1 - mv a5,a0 - mv a0,a1 - bne a4,zero,.L2 - mv a0,a5 -.L2: - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibge-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibge-ventana.c deleted file mode 100644 index 608bb9123fb0..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibge-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdige (int_t w, int_t x, int_t y, int_t z) -{ - return w >= x ? y : z; -} - -/* Expect branched assembly like: - - blt a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibgeu-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibgeu-ventana.c deleted file mode 100644 index ce8670c60cfd..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibgeu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (DI))) int_t; - -int_t -movdigeu (int_t w, int_t x, int_t y, int_t z) -{ - return w >= x ? y : z; -} - -/* Expect branched assembly like: - - bltu a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibgt-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibgt-ventana.c deleted file mode 100644 index 5bd50a4d8956..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibgt-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdigt (int_t w, int_t x, int_t y, int_t z) -{ - return w > x ? y : z; -} - -/* Expect branched assembly like: - - ble a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibgtu-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibgtu-ventana.c deleted file mode 100644 index 85b2dc2246d1..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibgtu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (DI))) int_t; - -int_t -movdigtu (int_t w, int_t x, int_t y, int_t z) -{ - return w > x ? y : z; -} - -/* Expect branched assembly like: - - bleu a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdible-ventana.c b/gcc/testsuite/gcc.target/riscv/movdible-ventana.c deleted file mode 100644 index a1d270a6bc31..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdible-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdile (int_t w, int_t x, int_t y, int_t z) -{ - return w <= x ? y : z; -} - -/* Expect branched assembly like: - - bgt a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibleu-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibleu-ventana.c deleted file mode 100644 index 7b7fccbdc767..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibleu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (DI))) int_t; - -int_t -movdileu (int_t w, int_t x, int_t y, int_t z) -{ - return w <= x ? y : z; -} - -/* Expect branched assembly like: - - bgtu a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdiblt-ventana.c b/gcc/testsuite/gcc.target/riscv/movdiblt-ventana.c deleted file mode 100644 index 22028f0bc53d..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdiblt-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdilt (int_t w, int_t x, int_t y, int_t z) -{ - return w < x ? y : z; -} - -/* Expect branched assembly like: - - bge a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibltu-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibltu-ventana.c deleted file mode 100644 index 16ec46cfe746..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibltu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (DI))) int_t; - -int_t -movdiltu (int_t w, int_t x, int_t y, int_t z) -{ - return w < x ? y : z; -} - -/* Expect branched assembly like: - - bgeu a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibne-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibne-ventana.c deleted file mode 100644 index 88e5690f17a7..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdibne-ventana.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdine (int_t w, int_t x, int_t y, int_t z) -{ - return w != x ? y : z; -} - -/* Expect branched assembly like: - - beq a0,a1,.L3 - mv a0,a2 - ret -.L3: - mv a0,a3 - ret - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\ssub\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdieq-ventana.c b/gcc/testsuite/gcc.target/riscv/movdieq-ventana.c deleted file mode 100644 index 7a9c78ddfee9..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdieq-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdieq (int_t w, int_t x, int_t y, int_t z) -{ - return w == x ? y : z; -} - -/* Expect branchless assembly like: - - sub a1,a0,a1 - vt.maskc a3,a3,a1 - vt.maskcn a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdifeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movdifeq-ventana.c deleted file mode 100644 index 13f430d2bc76..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdifeq-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdifeq (double w, double x, int_t y, int_t z) -{ - return w == x ? y : z; -} - -/* Expect branchless assembly like: - - feq.d a5,fa0,fa1 - vt.maskcn a1,a1,a5 - vt.maskc a0,a0,a5 - or a0,a0,a1 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdifge-ventana.c b/gcc/testsuite/gcc.target/riscv/movdifge-ventana.c deleted file mode 100644 index 618a6267646b..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdifge-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdifge (double w, double x, int_t y, int_t z) -{ - return w >= x ? y : z; -} - -/* Expect branchless assembly like: - - fge.d a5,fa0,fa1 - vt.maskc a0,a0,a5 - vt.maskcn a5,a1,a5 - or a0,a5,a0 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdifgt-ventana.c b/gcc/testsuite/gcc.target/riscv/movdifgt-ventana.c deleted file mode 100644 index b6b84e25c2cf..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdifgt-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdifgt (double w, double x, int_t y, int_t z) -{ - return w > x ? y : z; -} - -/* Expect branchless assembly like: - - fgt.d a5,fa0,fa1 - vt.maskc a0,a0,a5 - vt.maskcn a5,a1,a5 - or a0,a5,a0 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdifle-ventana.c b/gcc/testsuite/gcc.target/riscv/movdifle-ventana.c deleted file mode 100644 index 759005c78f27..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdifle-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdifle (double w, double x, int_t y, int_t z) -{ - return w <= x ? y : z; -} - -/* Expect branchless assembly like: - - fle.d a5,fa0,fa1 - vt.maskc a0,a0,a5 - vt.maskcn a5,a1,a5 - or a0,a5,a0 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdiflt-ventana.c b/gcc/testsuite/gcc.target/riscv/movdiflt-ventana.c deleted file mode 100644 index b89ddaa312fe..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdiflt-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdiflt (double w, double x, int_t y, int_t z) -{ - return w < x ? y : z; -} - -/* Expect branchless assembly like: - - flt.d a5,fa0,fa1 - vt.maskc a0,a0,a5 - vt.maskcn a5,a1,a5 - or a0,a5,a0 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdifne-ventana.c b/gcc/testsuite/gcc.target/riscv/movdifne-ventana.c deleted file mode 100644 index eb22c84338fe..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdifne-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdifne (double w, double x, int_t y, int_t z) -{ - return w != x ? y : z; -} - -/* Expect branchless assembly like: - - feq.d a5,fa0,fa1 - vt.maskc a1,a1,a5 - vt.maskcn a0,a0,a5 - or a0,a0,a1 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdige-ventana.c b/gcc/testsuite/gcc.target/riscv/movdige-ventana.c deleted file mode 100644 index bbf02628412e..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdige-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdige (int_t w, int_t x, int_t y, int_t z) -{ - return w >= x ? y : z; -} - -/* Expect branchless assembly like: - - slt a1,a0,a1 - vt.maskc a3,a3,a1 - vt.maskcn a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdigeu-ventana.c b/gcc/testsuite/gcc.target/riscv/movdigeu-ventana.c deleted file mode 100644 index 61a429a6ff64..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdigeu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (DI))) int_t; - -int_t -movdigeu (int_t w, int_t x, int_t y, int_t z) -{ - return w >= x ? y : z; -} - -/* Expect branchless assembly like: - - sltu a1,a0,a1 - vt.maskc a3,a3,a1 - vt.maskcn a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdigt-ventana.c b/gcc/testsuite/gcc.target/riscv/movdigt-ventana.c deleted file mode 100644 index 86d4cd4f8c06..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdigt-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdigt (int_t w, int_t x, int_t y, int_t z) -{ - return w > x ? y : z; -} - -/* Expect branchless assembly like: - - sgt a1,a0,a1 - vt.maskcn a3,a3,a1 - vt.maskc a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdigtu-ventana.c b/gcc/testsuite/gcc.target/riscv/movdigtu-ventana.c deleted file mode 100644 index e1da99e5c780..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdigtu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (DI))) int_t; - -int_t -movdigtu (int_t w, int_t x, int_t y, int_t z) -{ - return w > x ? y : z; -} - -/* Expect branchless assembly like: - - sgtu a1,a0,a1 - vt.maskcn a3,a3,a1 - vt.maskc a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdile-ventana.c b/gcc/testsuite/gcc.target/riscv/movdile-ventana.c deleted file mode 100644 index 67ed3d9f2b04..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdile-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdile (int_t w, int_t x, int_t y, int_t z) -{ - return w <= x ? y : z; -} - -/* Expect branchless assembly like: - - sgt a1,a0,a1 - vt.maskc a3,a3,a1 - vt.maskcn a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdileu-ventana.c b/gcc/testsuite/gcc.target/riscv/movdileu-ventana.c deleted file mode 100644 index 6147f8e600da..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdileu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (DI))) int_t; - -int_t -movdileu (int_t w, int_t x, int_t y, int_t z) -{ - return w <= x ? y : z; -} - -/* Expect branchless assembly like: - - sgtu a1,a0,a1 - vt.maskc a3,a3,a1 - vt.maskcn a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdilt-ventana.c b/gcc/testsuite/gcc.target/riscv/movdilt-ventana.c deleted file mode 100644 index 94ed75aeb179..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdilt-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdilt (int_t w, int_t x, int_t y, int_t z) -{ - return w < x ? y : z; -} - -/* Expect branchless assembly like: - - slt a1,a0,a1 - vt.maskcn a3,a3,a1 - vt.maskc a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdiltu-ventana.c b/gcc/testsuite/gcc.target/riscv/movdiltu-ventana.c deleted file mode 100644 index 52dfd1f77584..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdiltu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (DI))) int_t; - -int_t -movdiltu (int_t w, int_t x, int_t y, int_t z) -{ - return w < x ? y : z; -} - -/* Expect branchless assembly like: - - sltu a1,a0,a1 - vt.maskcn a3,a3,a1 - vt.maskc a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdine-ventana.c b/gcc/testsuite/gcc.target/riscv/movdine-ventana.c deleted file mode 100644 index baa0054ebea9..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movdine-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (DI))) int_t; - -int_t -movdine (int_t w, int_t x, int_t y, int_t z) -{ - return w != x ? y : z; -} - -/* Expect branchless assembly like: - - sub a1,a0,a1 - vt.maskcn a3,a3,a1 - vt.maskc a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibeq-ventana.c deleted file mode 100644 index e3ecb2d27713..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibeq-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsieq (int_t w, int_t x, int_t y, int_t z) -{ - return w == x ? y : z; -} - -/* Expect branched assembly like: - - bne a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\ssub\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibfeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfeq-ventana.c deleted file mode 100644 index 659917277664..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibfeq-ventana.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsifeq (double w, double x, int_t y, int_t z) -{ - return w == x ? y : z; -} - -/* Expect branched assembly like: - - feq.d a4,fa0,fa1 - mv a5,a0 - mv a0,a1 - beq a4,zero,.L2 - mv a0,a5 -.L2: - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c deleted file mode 100644 index 524a0f7c8883..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsifge (double w, double x, int_t y, int_t z) -{ - return w >= x ? y : z; -} - -/* Expect branched assembly like: - - fge.d a4,fa0,fa1 - mv a5,a0 - mv a0,a1 - beq a4,zero,.L2 - mv a0,a5 -.L2: - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c deleted file mode 100644 index df58aafa1669..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsifgt (double w, double x, int_t y, int_t z) -{ - return w > x ? y : z; -} - -/* Expect branched assembly like: - - fgt.d a4,fa0,fa1 - mv a5,a0 - mv a0,a1 - beq a4,zero,.L2 - mv a0,a5 -.L2: - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c deleted file mode 100644 index e32706f600f8..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsifle (double w, double x, int_t y, int_t z) -{ - return w <= x ? y : z; -} - -/* Expect branched assembly like: - - fle.d a4,fa0,fa1 - mv a5,a0 - mv a0,a1 - beq a4,zero,.L2 - mv a0,a5 -.L2: - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c deleted file mode 100644 index 3bbb17de0de2..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsiflt (double w, double x, int_t y, int_t z) -{ - return w < x ? y : z; -} - -/* Expect branched assembly like: - - flt.d a4,fa0,fa1 - mv a5,a0 - mv a0,a1 - beq a4,zero,.L2 - mv a0,a5 -.L2: - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c deleted file mode 100644 index 48010cde9232..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsifne (double w, double x, int_t y, int_t z) -{ - return w != x ? y : z; -} - -/* Expect branched assembly like: - - feq.d a4,fa0,fa1 - mv a5,a0 - mv a0,a1 - bne a4,zero,.L2 - mv a0,a5 -.L2: - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibge-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibge-ventana.c deleted file mode 100644 index 692f6b95a8b4..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibge-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsige (int_t w, int_t x, int_t y, int_t z) -{ - return w >= x ? y : z; -} - -/* Expect branched assembly like: - - blt a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibgeu-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibgeu-ventana.c deleted file mode 100644 index 8373415cbe34..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibgeu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (SI))) int_t; - -int_t -movsigeu (int_t w, int_t x, int_t y, int_t z) -{ - return w >= x ? y : z; -} - -/* Expect branched assembly like: - - bltu a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibgt-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibgt-ventana.c deleted file mode 100644 index cabf50fb87db..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibgt-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsigt (int_t w, int_t x, int_t y, int_t z) -{ - return w > x ? y : z; -} - -/* Expect branched assembly like: - - ble a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibgtu-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibgtu-ventana.c deleted file mode 100644 index 1400160d42d2..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibgtu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (SI))) int_t; - -int_t -movsigtu (int_t w, int_t x, int_t y, int_t z) -{ - return w > x ? y : z; -} - -/* Expect branched assembly like: - - bleu a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsible-ventana.c b/gcc/testsuite/gcc.target/riscv/movsible-ventana.c deleted file mode 100644 index dee1747b6927..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsible-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsile (int_t w, int_t x, int_t y, int_t z) -{ - return w <= x ? y : z; -} - -/* Expect branched assembly like: - - bgt a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibleu-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibleu-ventana.c deleted file mode 100644 index e128da45a005..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibleu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (SI))) int_t; - -int_t -movsileu (int_t w, int_t x, int_t y, int_t z) -{ - return w <= x ? y : z; -} - -/* Expect branched assembly like: - - bgtu a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsiblt-ventana.c b/gcc/testsuite/gcc.target/riscv/movsiblt-ventana.c deleted file mode 100644 index dded337dcdd8..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsiblt-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsilt (int_t w, int_t x, int_t y, int_t z) -{ - return w < x ? y : z; -} - -/* Expect branched assembly like: - - bge a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibltu-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibltu-ventana.c deleted file mode 100644 index 410563568869..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibltu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (SI))) int_t; - -int_t -movsiltu (int_t w, int_t x, int_t y, int_t z) -{ - return w < x ? y : z; -} - -/* Expect branched assembly like: - - bgeu a0,a1,.L2 - mv a3,a2 -.L2: - mv a0,a3 - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibne-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibne-ventana.c deleted file mode 100644 index cb54122ed356..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsibne-ventana.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsine (int_t w, int_t x, int_t y, int_t z) -{ - return w != x ? y : z; -} - -/* Expect branched assembly like: - - beq a0,a1,.L3 - mv a0,a2 - ret -.L3: - mv a0,a3 - ret - */ - -/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\ssub\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ -/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsieq-ventana.c b/gcc/testsuite/gcc.target/riscv/movsieq-ventana.c deleted file mode 100644 index 7bac3006629d..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsieq-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsieq (int_t w, int_t x, int_t y, int_t z) -{ - return w == x ? y : z; -} - -/* Expect branchless assembly like: - - sub a1,a0,a1 - vt.maskc a3,a3,a1 - vt.maskcn a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsifeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movsifeq-ventana.c deleted file mode 100644 index 31154aea0636..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsifeq-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsifeq (double w, double x, int_t y, int_t z) -{ - return w == x ? y : z; -} - -/* Expect branchless assembly like: - - feq.d a5,fa0,fa1 - vt.maskcn a1,a1,a5 - vt.maskc a0,a0,a5 - or a0,a0,a1 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsifge-ventana.c b/gcc/testsuite/gcc.target/riscv/movsifge-ventana.c deleted file mode 100644 index b644ea0d7a54..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsifge-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsifge (double w, double x, int_t y, int_t z) -{ - return w >= x ? y : z; -} - -/* Expect branchless assembly like: - - fge.d a5,fa0,fa1 - vt.maskc a0,a0,a5 - vt.maskcn a5,a1,a5 - or a0,a5,a0 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsifgt-ventana.c b/gcc/testsuite/gcc.target/riscv/movsifgt-ventana.c deleted file mode 100644 index 8c48ec84648a..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsifgt-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsifgt (double w, double x, int_t y, int_t z) -{ - return w > x ? y : z; -} - -/* Expect branchless assembly like: - - fgt.d a5,fa0,fa1 - vt.maskc a0,a0,a5 - vt.maskcn a5,a1,a5 - or a0,a5,a0 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsifle-ventana.c b/gcc/testsuite/gcc.target/riscv/movsifle-ventana.c deleted file mode 100644 index 0bf1210bf461..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsifle-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsifle (double w, double x, int_t y, int_t z) -{ - return w <= x ? y : z; -} - -/* Expect branchless assembly like: - - fle.d a5,fa0,fa1 - vt.maskc a0,a0,a5 - vt.maskcn a5,a1,a5 - or a0,a5,a0 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsiflt-ventana.c b/gcc/testsuite/gcc.target/riscv/movsiflt-ventana.c deleted file mode 100644 index f4bdb85a558c..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsiflt-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsiflt (double w, double x, int_t y, int_t z) -{ - return w < x ? y : z; -} - -/* Expect branchless assembly like: - - flt.d a5,fa0,fa1 - vt.maskc a0,a0,a5 - vt.maskcn a5,a1,a5 - or a0,a5,a0 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsifne-ventana.c b/gcc/testsuite/gcc.target/riscv/movsifne-ventana.c deleted file mode 100644 index 337f66293a96..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsifne-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsifne (double w, double x, int_t y, int_t z) -{ - return w != x ? y : z; -} - -/* Expect branchless assembly like: - - feq.d a5,fa0,fa1 - vt.maskc a1,a1,a5 - vt.maskcn a0,a0,a5 - or a0,a0,a1 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsige-ventana.c b/gcc/testsuite/gcc.target/riscv/movsige-ventana.c deleted file mode 100644 index aeebc40d0d4e..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsige-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsige (int_t w, int_t x, int_t y, int_t z) -{ - return w >= x ? y : z; -} - -/* Expect branchless assembly like: - - slt a1,a0,a1 - vt.maskc a3,a3,a1 - vt.maskcn a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsigeu-ventana.c b/gcc/testsuite/gcc.target/riscv/movsigeu-ventana.c deleted file mode 100644 index 726bf40fd9fd..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsigeu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (SI))) int_t; - -int_t -movsigeu (int_t w, int_t x, int_t y, int_t z) -{ - return w >= x ? y : z; -} - -/* Expect branchless assembly like: - - sltu a1,a0,a1 - vt.maskc a3,a3,a1 - vt.maskcn a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsigt-ventana.c b/gcc/testsuite/gcc.target/riscv/movsigt-ventana.c deleted file mode 100644 index 151b386e985f..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsigt-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsigt (int_t w, int_t x, int_t y, int_t z) -{ - return w > x ? y : z; -} - -/* Expect branchless assembly like: - - sgt a1,a0,a1 - vt.maskcn a3,a3,a1 - vt.maskc a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsigtu-ventana.c b/gcc/testsuite/gcc.target/riscv/movsigtu-ventana.c deleted file mode 100644 index f19d842e26f7..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsigtu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (SI))) int_t; - -int_t -movsigtu (int_t w, int_t x, int_t y, int_t z) -{ - return w > x ? y : z; -} - -/* Expect branchless assembly like: - - sgtu a1,a0,a1 - vt.maskcn a3,a3,a1 - vt.maskc a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsile-ventana.c b/gcc/testsuite/gcc.target/riscv/movsile-ventana.c deleted file mode 100644 index 9bb4d8ba082d..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsile-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsile (int_t w, int_t x, int_t y, int_t z) -{ - return w <= x ? y : z; -} - -/* Expect branchless assembly like: - - sgt a1,a0,a1 - vt.maskc a3,a3,a1 - vt.maskcn a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsileu-ventana.c b/gcc/testsuite/gcc.target/riscv/movsileu-ventana.c deleted file mode 100644 index 1bd51c03bce5..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsileu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (SI))) int_t; - -int_t -movsileu (int_t w, int_t x, int_t y, int_t z) -{ - return w <= x ? y : z; -} - -/* Expect branchless assembly like: - - sgtu a1,a0,a1 - vt.maskc a3,a3,a1 - vt.maskcn a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsilt-ventana.c b/gcc/testsuite/gcc.target/riscv/movsilt-ventana.c deleted file mode 100644 index 90d8a9727352..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsilt-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsilt (int_t w, int_t x, int_t y, int_t z) -{ - return w < x ? y : z; -} - -/* Expect branchless assembly like: - - slt a1,a0,a1 - vt.maskcn a3,a3,a1 - vt.maskc a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsiltu-ventana.c b/gcc/testsuite/gcc.target/riscv/movsiltu-ventana.c deleted file mode 100644 index 1cbfafa79bdc..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsiltu-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ - -typedef unsigned int __attribute__ ((mode (SI))) int_t; - -int_t -movsiltu (int_t w, int_t x, int_t y, int_t z) -{ - return w < x ? y : z; -} - -/* Expect branchless assembly like: - - sltu a1,a0,a1 - vt.maskcn a3,a3,a1 - vt.maskc a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsine-ventana.c b/gcc/testsuite/gcc.target/riscv/movsine-ventana.c deleted file mode 100644 index a294d1be5168..000000000000 --- a/gcc/testsuite/gcc.target/riscv/movsine-ventana.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-require-effective-target rv64 } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ -/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ - -typedef int __attribute__ ((mode (SI))) int_t; - -int_t -movsine (int_t w, int_t x, int_t y, int_t z) -{ - return w != x ? y : z; -} - -/* Expect branchless assembly like: - - sub a1,a0,a1 - vt.maskcn a3,a3,a1 - vt.maskc a1,a2,a1 - or a0,a1,a3 - */ - -/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ -/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ -/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ -/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ -/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr116240.c b/gcc/testsuite/gcc.target/riscv/pr116240.c index 7e3eaa2f5445..b643802710d9 100644 --- a/gcc/testsuite/gcc.target/riscv/pr116240.c +++ b/gcc/testsuite/gcc.target/riscv/pr116240.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-fwrapv -march=rv64imvxtheadcondmov_xventanacondops -mabi=lp64d" } */ +/* { dg-additional-options "-fwrapv -march=rv64imvxtheadcondmov_zicond -mabi=lp64d" } */ int a, b; void c() { diff --git a/gcc/testsuite/gcc.target/riscv/predef-30.c b/gcc/testsuite/gcc.target/riscv/predef-30.c deleted file mode 100644 index 9784b9ce5033..000000000000 --- a/gcc/testsuite/gcc.target/riscv/predef-30.c +++ /dev/null @@ -1,27 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64i_xventanacondops -mabi=lp64 -mcmodel=medlow -misa-spec=20191213" } */ - -int main () { - -#ifndef __riscv_arch_test -#error "__riscv_arch_test" -#endif - -#if __riscv_xlen != 64 -#error "__riscv_xlen" -#endif - -#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000)) -#error "__riscv_i" -#endif - -#if defined(__riscv_e) -#error "__riscv_e" -#endif - -#if !defined(__riscv_xventanacondops) -#error "__riscv_xventanacondops" -#endif - - return 0; -} diff --git a/gcc/testsuite/gcc.target/riscv/ventana-16122.c b/gcc/testsuite/gcc.target/riscv/ventana-16122.c deleted file mode 100644 index 59e6467b57c0..000000000000 --- a/gcc/testsuite/gcc.target/riscv/ventana-16122.c +++ /dev/null @@ -1,19 +0,0 @@ -/* { dg-do compile { target { rv64 } } } */ - -extern void NG (void); -typedef signed char int8_t; -typedef signed short int16_t; -typedef signed int int32_t; -void f74(void) { - int16_t x309 = 0x7fff; - volatile int32_t x310 = 0x7fffffff; - int8_t x311 = 59; - int16_t x312 = -0x8000; - static volatile int32_t t74 = 614992577; - - t74 = (x309==((x310^x311)%x312)); - - if (t74 != 0) { NG(); } else { ; } - -} - diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c deleted file mode 100644 index 862ad309b52c..000000000000 --- a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv32gc_xventanacondops -mabi=ilp32d" } */ -/* { dg-skip-if "" { *-*-* } {"-O0" "-Og"} } */ - -#include "zicond-primitiveSemantics.c" - -/* { dg-final { scan-assembler-not "vt\\.maskc\t" } } */ -/* { dg-final { scan-assembler-not "vt\\.maskcn\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c deleted file mode 100644 index 19bbcb6a5dfd..000000000000 --- a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */ -/* { dg-skip-if "" { *-*-* } {"-O0" "-Og"} } */ - -#include "zicond-primitiveSemantics.c" - -/* { dg-final { scan-assembler-times "vt\\.maskc\t" 6 } } */ -/* { dg-final { scan-assembler-times "vt\\.maskcn\t" 6 } } */ -/* { dg-final { scan-assembler-not {\mbeq} } } */ -/* { dg-final { scan-assembler-not {\mbne} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c deleted file mode 100644 index 634eff84f89d..000000000000 --- a/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ - -#include "zicond-xor-01.c" - -/* { dg-final { scan-assembler-times "vt\\.maskc\t" 1 } } */ -/* { dg-final { scan-assembler-times "xor\t" 1 } } */
