https://gcc.gnu.org/g:f7920ff75d7924bde524caabf5f6e7730c1a81ed
commit r17-5303-gf7920ff75d7924bde524caabf5f6e7730c1a81ed Author: Uros Bizjak <[email protected]> Date: Fri Oct 16 16:29:46 2026 +0200 i386: Clean up mul patterns Convert *umul<mode><dwi>3_1 to define_insn_and_split and merge the standalone define_split that converted the BMI2 "mul" alternative to the flags-independent mulx pattern into it. The split conditions are unchanged. Keeping the splitter next to the insn it applies to makes the relationship between the "#" alternative and its split obvious. While moving the splitter, remove the assignment to operands[5]. The split pattern has no corresponding match_dup, so the value was never used and had no business being stored outside the declared operands. Also remove the !(MEM_P (operands[1]) && MEM_P (operands[2])) checks from the conditions of *umul<mode><dwi>3_1, *mul<mode><dwi>3_1<nf_name> and *<u>mulqihi3_1<nf_name>. Operand 1 of these patterns is a register_operand, so it can never be a MEM and the checks are redundant. No functional changes intended. gcc/ChangeLog: * config/i386/i386.md (*umul<mode><dwi>3_1): Change to define_insn_and_split. Merge in the define_split that converts mul to the mulx pattern. Remove redundant !(MEM_P (operands[1]) && MEM_P (operands[2])) condition. Do not assign operands[5] in the split, it has no matching match_dup. (*mul<mode><dwi>3_1<nf_name>): Remove redundant !(MEM_P (operands[1]) && MEM_P (operands[2])) condition. (*<u>mulqihi3_1<nf_name>): Ditto. Diff: --- gcc/config/i386/i386.md | 36 ++++++++++-------------------------- 1 file changed, 10 insertions(+), 26 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index ffd588e67cc6..4935e12cfc14 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -11813,7 +11813,7 @@ operands[1] = operands[4]; }) -(define_insn "*umul<mode><dwi>3_1" +(define_insn_and_split "*umul<mode><dwi>3_1" [(set (match_operand:<DWI> 0 "register_operand" "=r,A") (mult:<DWI> (zero_extend:<DWI> @@ -11821,10 +11821,17 @@ (zero_extend:<DWI> (match_operand:DWIH 2 "nonimmediate_operand" "rm,rm")))) (clobber (reg:CC FLAGS_REG))] - "!(MEM_P (operands[1]) && MEM_P (operands[2]))" + "" "@ # mul{<imodesuffix>}\t%2" + "TARGET_BMI2 && reload_completed + && REGNO (operands[1]) == DX_REG" + [(parallel [(set (match_dup 3) + (mult:DWIH (match_dup 1) (match_dup 2))) + (set (match_dup 4) + (umul_highpart:DWIH (match_dup 1) (match_dup 2)))])] + "split_double_mode (<DWI>mode, &operands[0], 1, &operands[3], &operands[4]);" [(set_attr "isa" "bmi2,*") (set_attr "type" "imulx,imul") (set_attr "length_immediate" "*,0") @@ -11839,27 +11846,6 @@ (set_attr "prefix" "vex,orig") (set_attr "mode" "<MODE>")]) -;; Convert mul to the mulx pattern to avoid flags dependency. -(define_split - [(set (match_operand:<DWI> 0 "register_operand") - (mult:<DWI> - (zero_extend:<DWI> - (match_operand:DWIH 1 "register_operand")) - (zero_extend:<DWI> - (match_operand:DWIH 2 "nonimmediate_operand")))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_BMI2 && reload_completed - && REGNO (operands[1]) == DX_REG" - [(parallel [(set (match_dup 3) - (mult:DWIH (match_dup 1) (match_dup 2))) - (set (match_dup 4) - (umul_highpart:DWIH (match_dup 1) (match_dup 2)))])] -{ - split_double_mode (<DWI>mode, &operands[0], 1, &operands[3], &operands[4]); - - operands[5] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT); -}) - (define_insn "*mul<mode><dwi>3_1<nf_name>" [(set (match_operand:<DWI> 0 "register_operand" "=A") (mult:<DWI> @@ -11867,8 +11853,7 @@ (match_operand:DWIH 1 "register_operand" "%a")) (sign_extend:<DWI> (match_operand:DWIH 2 "nonimmediate_operand" "rm"))))] - "!(MEM_P (operands[1]) && MEM_P (operands[2])) - && <nf_condition>" + "<nf_condition>" "<nf_prefix>imul{<imodesuffix>}\t%2" [(set_attr "type" "imul") (set_attr "length_immediate" "0") @@ -11888,7 +11873,6 @@ (any_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))] "TARGET_QIMODE_MATH - && !(MEM_P (operands[1]) && MEM_P (operands[2])) && <nf_condition>" "<nf_prefix><sgnprefix>mul{b}\t%2" [(set_attr "type" "imul")
